From ce6bff58d244dfd901819bba819d3716c1d9a58a Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Fri, 6 Nov 2020 11:01:01 -0700 Subject: [PATCH] Allow TGL mixed topology to have mismatched SPD length Change-Id: I1a0d66ed580cf2f11c61500b801335500b35c603 --- src/soc/intel/tigerlake/meminit.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 1b441c7b81..13ae4e2cf4 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -378,7 +378,7 @@ void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, read_sodimm_spd(info, &spd_sodimm_blk); if ((info->topology == MIXED) && (mem_cfg->MemorySpdDataLen != spd_sodimm_blk.len)) - die("Mixed topology has incorrect length.\n"); + printk(BIOS_ERR, "Mixed topology has incorrect length: %d != %d.\n", mem_cfg->MemorySpdDataLen, spd_sodimm_blk.len); else mem_cfg->MemorySpdDataLen = spd_sodimm_blk.len; }