exynos5-common: get rid of displayport trial code
This was a first pass at display port support, we have realized that it was ultimately a bad path. The display hardware is intimately tied into a specific cpu and mainboard combination, and the code has to be elsewhere. The devicetree formatting is ugly, but it matters not: it's changing soon. Change-Id: Iddce54f9e7219a7569315565fac65afbbe0edd29 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/3029 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Ronald G. Minnich
committed by
Stefan Reinauer
Stefan Reinauer
parent
5f3754e66d
commit
ce801b55fa
@@ -21,5 +21,3 @@ ramstage-y += gpio.c
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ramstage-y += i2c.c
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ramstage-y += s5p-dp-reg.c
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ramstage-y += exynos-fb.c
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subdirs-y += displayport
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@@ -1,2 +0,0 @@
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config EXYNOS_DISPLAYPORT
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bool
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@@ -1,2 +0,0 @@
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ramstage-$(CONFIG_EXYNOS_DISPLAYPORT) += displayport.c
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@@ -1,40 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H
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#define CPU_SAMSUNG_EXYNOS5_COMMON_DISPLAYPORT_H
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struct cpu_samsung_exynos5_common_displayport_config {
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/* special magic numbers! */
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int clkval_f;
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int upper_margin;
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int lower_margin;
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int vsync;
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int left_margin;
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int right_margin;
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int hsync;
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int xres;
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int yres;
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int bpp;
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u32 lcdbase;
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};
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#endif /* CPU_SAMSUNG_EXYNOS5-COMMON_DISPLAYPORT_H */
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@@ -1,107 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <delay.h>
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#include <arch/io.h>
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#include <device/device.h>
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/* we distinguish a display port device from a raw graphics device because there are
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* dramatic differences in startup depending on graphics usage. To make startup fast
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* and easier to understand and debug we explicitly name this common case. The alternate
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* approach, involving lots of machine and callbacks, is hard to debug and verify.
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*/
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static void exynos_displayport_init(void)
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{
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struct cpu_samsung_exynos5_common_displayport_config *conf = dev->chip_info;
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/* put these on the stack. If, at some point, we want to move this code to a
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* pre-ram stage, it will be much easier.
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*/
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vidinfo_t vi;
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struct exynos5_fimd_panel panel;
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void *lcdbase;
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memset(vi, 0, sizeof(vi));
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memset(panel, 0, sizeof(panel));
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panel.is_dp = 1; /* Display I/F is eDP */
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/* while it is true that we did a memset to zero,
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* we leave some 'set to zero' entries here to make
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* it clear what's going on. Graphics is confusing.
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*/
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panel.is_mipi = 0;
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panel.fixvclk = 0;
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panel.ivclk = 0;
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panel.clkval_f = conf->clkval_f;
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panel.upper_margin = conf->upper_margin;
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panel.lower_margin = conf->lower_margin;
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panel.vsync = conf->vsync;
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panel.left_margin = conf->left_margin;
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panel.right_margin = conf->right_margin;
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panel.hsync = conf->hsync;
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vi->vl_col = conf->xres;
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vi->fl_row = conf->yres;
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vi->vl_bpix = conf->bpp;
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vi->cmap = cbmem_reserve(64*1024); /* The size is a magic number from hardware. */
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lcdbase = conf->lcdbase;
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printk(BIOS_DEBUG, "Initializing exynos VGA\n");
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ret = lcd_ctrl_init(&vi, &panel, lcdbase);
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#if 0
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ret = board_dp_lcd_vdd(blob, &wait_ms);
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ret = board_dp_bridge_setup(blob, &wait_ms);
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while (tries < 5) {
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ret = board_dp_bridge_init(blob, &wait_ms);
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ret = board_dp_hotplug(blob, &wait_ms);
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if (ret) {
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ret = board_dp_bridge_reset(blob, &wait_ms);
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continue;
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}
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ret = dp_controller_init(blob, &wait_ms);
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ret = board_dp_backlight_vdd(blob, &wait_ms);
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ret = board_dp_backlight_pwm(blob, &wait_ms);
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ret = board_dp_backlight_en(blob, &wait_ms);
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}
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#endif
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}
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static void exynos_displayport_noop(device_t dummy)
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{
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}
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static struct device_operations exynos_displayport_operations = {
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.read_resources = exynos_displayport_noop,
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.set_resources = exynos_displayport_noop,
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.enable_resources = exynos_displayport_noop,
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.init = exynos_displayport_init,
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.scan_bus = exynos_displayport_noop,
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};
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static void exynos_displayport_enable(struct device *dev)
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{
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if (dev->link_list != NULL)
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dev->ops = &exynos_displayport_operations;
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}
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struct chip_operations drivers_i2c_exynos_displayport_ops = {
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CHIP_NAME("exynos displayport")
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.enable_dev = exynos_displayport_enable;
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};
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@@ -28,19 +28,5 @@ device domain 0 on
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device i2c 6 on end # ?
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device i2c 9 on end # ?
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end
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chip cpu/samsung/exynos5-common/displayport
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register "xres" = "1366"
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register "yres" = "768"
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register "bpp" = "16"
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# complex magic timing!
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register "clkval_f" = "2"
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register "upper_margin" = "14"
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register "lower_margin" = "3"
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register "vsync" = "5"
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register "left_margin" = "80"
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register "right_margin" = "48"
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register "hsync" = "32"
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register "lcdbase" = "0x10000000"
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end
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end
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end
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