soc/intel/quark: Add C bootblock
Add a bootblock which builds with C_ENVIRONMENT_BOOTBLOCK selected. This is the first piece in supporting FSP 2.0. Move esraminit from romstage into the bootblock. Replace cache_as_ram with car_stage_entry.S and code in romstage.c TEST=Build and run on Galileo Gen2 Change-Id: I14d2af2adb6e75d4bff1ebfb863196df04d07daf Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15132 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Lee Leahy
77
src/soc/intel/quark/bootblock/bootblock.c
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77
src/soc/intel/quark/bootblock/bootblock.c
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@@ -0,0 +1,77 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015-2016 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <device/pci_def.h>
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#include <program_loading.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/reg_access.h>
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static const struct reg_script clear_smi_and_wake_events[] = {
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/* Clear any SMI or wake events */
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REG_GPE0_READ(R_QNC_GPE0BLK_GPE0S),
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REG_GPE0_READ(R_QNC_GPE0BLK_SMIS),
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REG_GPE0_OR(R_QNC_GPE0BLK_GPE0S, B_QNC_GPE0BLK_GPE0S_ALL),
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REG_GPE0_OR(R_QNC_GPE0BLK_SMIS, B_QNC_GPE0BLK_SMIS_ALL),
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REG_SCRIPT_END
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};
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static const struct reg_script legacy_gpio_init[] = {
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/* Temporarily enable the legacy GPIO controller */
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REG_PCI_WRITE32(R_QNC_LPC_GBA_BASE, IO_ADDRESS_VALID
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| LEGACY_GPIO_BASE_ADDRESS),
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/* Temporarily enable the GPE controller */
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REG_PCI_WRITE32(R_QNC_LPC_GPE0BLK, IO_ADDRESS_VALID
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| GPE0_BASE_ADDRESS),
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REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_IO),
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REG_SCRIPT_END
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};
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static const struct reg_script i2c_gpio_controller_init[] = {
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/* Temporarily enable the GPIO controller */
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REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, I2C_BASE_ADDRESS),
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REG_PCI_WRITE32(PCI_BASE_ADDRESS_1, GPIO_BASE_ADDRESS),
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REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
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REG_SCRIPT_END
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};
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static const struct reg_script hsuart_init[] = {
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/* Enable the HSUART */
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REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, UART_BASE_ADDRESS),
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REG_PCI_OR8(PCI_COMMAND, PCI_COMMAND_MEMORY),
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REG_SCRIPT_END
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};
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void bootblock_soc_early_init(void)
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{
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/* Initialize the controllers */
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reg_script_run_on_dev(I2CGPIO_BDF, i2c_gpio_controller_init);
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reg_script_run_on_dev(LPC_BDF, legacy_gpio_init);
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/* Enable the HSUART */
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if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART0))
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reg_script_run_on_dev(HSUART0_BDF, hsuart_init);
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if (IS_ENABLED(CONFIG_ENABLE_BUILTIN_HSUART1))
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reg_script_run_on_dev(HSUART1_BDF, hsuart_init);
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}
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void platform_prog_run(struct prog *prog)
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{
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/* Display the program entry point */
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printk(BIOS_SPEW, "Calling %s, 0x%p(0x%p)\n", prog->name,
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prog->entry, prog->arg);
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}
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539
src/soc/intel/quark/bootblock/esram_init.S
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539
src/soc/intel/quark/bootblock/esram_init.S
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@@ -0,0 +1,539 @@
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/** @file
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*
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* Copyright (C) 2015-2016, Intel Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* * Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* * Neither the name of Intel Corporation nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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**/
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#include <cpu/x86/cr.h>
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#include <cpu/x86/post_code.h>
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#include <soc/QuarkNcSocId.h>
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#include <soc/sd.h>
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.macro RET32
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jmp *%esp
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.endm
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/* ROM/SPI/MEMORY Definitions */
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.equ QUARK_DDR3_MEM_BASE_ADDRESS, (0x000000000) /* Memory Base Address = 0 */
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.equ QUARK_MAX_DDR3_MEM_SIZE_BYTES, (0x80000000) /* DDR3 Memory Size = 2GB */
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.equ QUARK_ESRAM_MEM_BASE_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \
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+ QUARK_MAX_DDR3_MEM_SIZE_BYTES) /* eSRAM Memory above DDR3 */
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.equ QUARK_ESRAM_MEM_SIZE_BYTES, (0x00080000) /* eSRAM Memory Size = 512K */
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.equ QUARK_STACK_SIZE_BYTES, (0x008000) /* Quark stack size = 32K */
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.equ QUARK_STACK_BASE_ADDRESS, (QUARK_ESRAM_MEM_BASE_ADDRESS \
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+ QUARK_ESRAM_MEM_SIZE_BYTES \
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- QUARK_STACK_SIZE_BYTES) /* Top of eSRAM - stack size */
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.equ QUARK_CMH_SIZE_BYTES, (0x0400) /* Quark Module Header size */
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.equ QUARK_ESRAM_STAGE1_BASE_ADDRESS, (QUARK_ESRAM_MEM_BASE_ADDRESS \
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+ QUARK_CMH_SIZE_BYTES) /* Start of Stage1 code in eSRAM */
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/* RTC/CMOS definitions */
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.equ RTC_INDEX, (0x70)
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.equ NMI_DISABLE, (0x80) /* Bit7=1 disables NMI */
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.equ RTC_DATA, (0x71)
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/* PCI Configuration definitions (Datasheet 5.5.1) */
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.equ PCI_CFG, (0x80000000) /* PCI configuration access mechanism */
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.equ PCI_ADDRESS_PORT, (0xCF8)
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.equ PCI_DATA_PORT, (0xCFC)
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/* Quark PCI devices */
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.equ HOST_BRIDGE_PFA, (0 << 11) /* B0:D0:F0 (Host Bridge) */
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.equ ILB_PFA, (0x1F << 11) /* B0:D31:F0 (Legacy Block) */
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/* ILB PCI Config Registers */
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.equ BDE, (0x0D4) /* BIOS Decode Enable register */
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.equ DECODE_ALL_REGIONS_ENABLE, (0xFF000000) /* Decode all BIOS ranges */
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/* iLB Reset Register */
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.equ ILB_RESET_REG, (0x0CF9)
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.equ CF9_WARM_RESET, (0x02)
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.equ CF9_COLD_RESET, (0x08)
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/* Memory Arbiter Config Registers */
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.equ AEC_CTRL_OFFSET, (0x00)
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/* Host Bridge Config Registers */
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.equ HMBOUND_OFFSET, (0x08)
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.equ HMBOUND_ADDRESS, (QUARK_DDR3_MEM_BASE_ADDRESS \
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+ QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES)
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.equ HECREG_OFFSET, (0x09)
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.equ EC_BASE, (0xE0000000)
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.equ EC_ENABLE, (0x01)
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/* Memory Manager Config Registers */
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.equ ESRAM_ADDRESS_2G, (0x10000080)
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.equ BIMRVCTL_OFFSET, (0x19)
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.equ ENABLE_IMR_INTERRUPT, (0x80000000)
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/* SOC UNIT Debug Registers */
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.equ CFGSTICKY_W1_OFFSET, (0x50)
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.equ FORCE_COLD_RESET, (0x00000001)
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.equ CFGSTICKY_RW_OFFSET, (0x51)
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.equ RESET_FOR_ESRAM_LOCK, (0x00000020)
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.equ RESET_FOR_HMBOUND_LOCK, (0x00000040)
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.equ CFGNONSTICKY_W1_OFFSET, (0x52)
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.equ FORCE_WARM_RESET, (0x00000001)
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.global bootblock_save_bist_and_timestamp
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bootblock_save_bist_and_timestamp:
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/* eax: Low 32-bits of timestamp
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* ebx: BIST result
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* ebp: return address
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* edx: High 32-bits of timestamp
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*/
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/* No values to save since Quark does not generate a BIST value
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* and the timestamp is not saved since future expansion in
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* bootblock_crt0.S could use ebp and edi. This code prevents
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* the use of the MMx registers by the default implementation.
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*/
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jmp *%ebp
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.global bootblock_pre_c_entry
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bootblock_pre_c_entry:
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/* Get the timestamp since value from bootblock_crt0.S was discarded */
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rdtsc
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movl %eax, %ebp
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movl %edx, %edi
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/* Registers:
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* ebp: Low 32-bits of timestamp
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* edi: High 32-bits of timestamp
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*/
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setup_esram:
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/* Ensure cache is disabled. */
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movl %cr0, %eax
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orl $(CR0_CD | CR0_NW), %eax
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invd
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movl %eax, %cr0
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/*
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* Disable NMI operation
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* Good convention suggests you should read back RTC data port after
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* accessing the RTC index port.
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*/
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movb $(NMI_DISABLE), %al
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movw $(RTC_INDEX), %dx
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outb %al, %dx
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movw $(RTC_DATA), %dx
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inb %dx, %al
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/* Disable SMI (Disables SMI wire, not SMI messages) */
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movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \
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| (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
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| (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx
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leal L1, %esp
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jmp stackless_SideBand_Read
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L1:
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andl $(~SMI_EN), %eax
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movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
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| (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
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| (QNC_MSG_FSBIC_REG_HMISC << QNC_MCR_REG_OFFSET)), %ecx
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leal L2, %esp
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jmp stackless_SideBand_Write
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L2:
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/*
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* Before we get going, check SOC Unit Registers to see if we are
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* required to issue a warm/cold reset
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*/
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movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
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| (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
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| (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
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leal L3, %esp
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jmp stackless_SideBand_Read
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L3:
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andl $(FORCE_WARM_RESET), %eax
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jz TestForceColdReset /* No warm reset - branch */
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jmp IssueWarmReset
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TestForceColdReset:
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movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
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| (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
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| (CFGNONSTICKY_W1_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
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leal L4, %esp
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jmp stackless_SideBand_Read
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L4:
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andl $(FORCE_COLD_RESET), %eax
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jz TestHmboundLock /* No cold reset - branch */
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jmp IssueColdReset
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/* Before setting HMBOUND, check it's not locked */
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TestHmboundLock:
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movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \
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| (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
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| (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
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leal L5, %esp
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jmp stackless_SideBand_Read
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L5:
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andl $(HMBOUND_LOCK), %eax
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jz ConfigHmbound /* Good configuration - branch */
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/* Failed to config - store sticky bit debug */
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movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
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| (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
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| (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
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leal L6, %esp
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jmp stackless_SideBand_Read
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L6:
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orl $(RESET_FOR_HMBOUND_LOCK), %eax
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movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
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| (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
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| (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
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leal L7, %esp
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jmp stackless_SideBand_Write
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L7:
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jmp IssueWarmReset
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/* Set up the HMBOUND register */
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ConfigHmbound:
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movl $(HMBOUND_ADDRESS), %eax /* Data (Set HMBOUND location) */
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movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
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| (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
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| (HMBOUND_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
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leal L8, %esp
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jmp stackless_SideBand_Write
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L8:
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/*
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* Enable interrupts to Remote Management Unit when a IMR/SMM/HMBOUND
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* violation occurs.
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*/
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movl $(ENABLE_IMR_INTERRUPT), %eax /* Set interrupt enable mask */
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movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
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| (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
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| (BIMRVCTL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
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leal L9, %esp
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jmp stackless_SideBand_Write
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L9:
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/* Move eSRAM memory to 2GB */
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movl $(ESRAM_ADDRESS_2G), %eax /* Data (Set eSRAM location) */
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movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
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| (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
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| (QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK \
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<< QNC_MCR_REG_OFFSET)), %ecx
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leal L10, %esp
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jmp stackless_SideBand_Write
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L10:
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/* Check that we're not blocked from setting the config that we want. */
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movl $((QUARK_OPCODE_READ << QNC_MCR_OP_OFFSET) \
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| (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
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| (QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK \
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<< QNC_MCR_REG_OFFSET)), %ecx
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leal L11, %esp
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jmp stackless_SideBand_Read
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L11:
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andl $(BLOCK_ENABLE_PG), %eax
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jnz ConfigPci /* Good configuration - branch */
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/* Failed to config - store sticky bit debug */
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movl $((QUARK_ALT_OPCODE_READ << QNC_MCR_OP_OFFSET) \
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| (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
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| (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
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leal L12, %esp
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jmp stackless_SideBand_Read
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L12:
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orl $(RESET_FOR_ESRAM_LOCK), %eax
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movl $((QUARK_ALT_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
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| (QUARK_SCSS_SOC_UNIT_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
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| (CFGSTICKY_RW_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
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leal L13, %esp
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jmp stackless_SideBand_Write
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L13:
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jmp IssueWarmReset
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/* Enable PCIEXBAR */
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ConfigPci:
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movl $(EC_BASE + EC_ENABLE), %eax /* Data */
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movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
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| (QUARK_NC_MEMORY_ARBITER_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
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| (AEC_CTRL_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
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leal L14, %esp
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jmp stackless_SideBand_Write
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L14:
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movl $(EC_BASE + EC_ENABLE), %eax /* Data */
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movl $((QUARK_OPCODE_WRITE << QNC_MCR_OP_OFFSET) \
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| (QUARK_NC_HOST_BRIDGE_SB_PORT_ID << QNC_MCR_PORT_OFFSET) \
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| (HECREG_OFFSET << QNC_MCR_REG_OFFSET)), %ecx
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leal L15, %esp
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jmp stackless_SideBand_Write
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L15:
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/* Open up full 8MB SPI decode */
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movl $(PCI_CFG | ILB_PFA | BDE), %ebx /* PCI config address */
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movl $(DECODE_ALL_REGIONS_ENABLE), %eax
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leal L16, %esp
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jmp stackless_PCIConfig_Write
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L16:
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jmp esram_init_done
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IssueWarmReset:
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/* Issue Warm Reset request to Remote Management Unit via iLB */
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||||
movw $(CF9_WARM_RESET), %ax
|
||||
movw $(ILB_RESET_REG), %dx
|
||||
outw %ax, %dx
|
||||
jmp . /* Stay here until we are reset. */
|
||||
|
||||
IssueColdReset:
|
||||
/* Issue Cold Reset request to Remote Management Unit via iLB */
|
||||
movw $(CF9_COLD_RESET), %ax
|
||||
movw $(ILB_RESET_REG), %dx
|
||||
outw %ax, %dx
|
||||
jmp . /* Stay here until we are reset. */
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Procedure: stackless_SideBand_Read
|
||||
*
|
||||
* Input: esp - return address
|
||||
* ecx[15:8] - Register offset
|
||||
* ecx[23:16] - Port ID
|
||||
* ecx[31:24] - Opcode
|
||||
*
|
||||
* Output: eax - Data read
|
||||
*
|
||||
* Destroys: eax
|
||||
* ebx
|
||||
* cl
|
||||
* esi
|
||||
*
|
||||
* Description:
|
||||
* Perform requested sideband read
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
stackless_SideBand_Read:
|
||||
|
||||
movl %esp, %esi /* Save the return address */
|
||||
|
||||
/* Load the SideBand Packet Register to generate the transaction */
|
||||
movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR), %ebx
|
||||
movb $QNC_MCR_BYTE_ENABLES, %cl /* Set all Byte Enable bits */
|
||||
xchgl %ecx, %eax
|
||||
leal L17, %esp
|
||||
jmp stackless_PCIConfig_Write
|
||||
L17:
|
||||
xchgl %ecx, %eax
|
||||
|
||||
/* Read the SideBand Data Register */
|
||||
movl $(PCI_CFG | HOST_BRIDGE_PFA | (QNC_ACCESS_PORT_MDR)), %ebx
|
||||
leal L18, %esp
|
||||
jmp stackless_PCIConfig_Read
|
||||
L18:
|
||||
|
||||
movl %esi, %esp /* Restore the return address */
|
||||
RET32
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Procedure: stackless_SideBand_Write
|
||||
*
|
||||
* Input: esp - return address
|
||||
* eax - Data
|
||||
* ecx[15:8] - Register offset
|
||||
* ecx[23:16] - Port ID
|
||||
* ecx[31:24] - Opcode
|
||||
*
|
||||
* Output: None
|
||||
*
|
||||
* Destroys: ebx
|
||||
* cl
|
||||
* esi
|
||||
*
|
||||
* Description:
|
||||
* Perform requested sideband write
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
stackless_SideBand_Write:
|
||||
|
||||
movl %esp, %esi /* Save the return address */
|
||||
|
||||
/* Load the SideBand Data Register with the data */
|
||||
movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MDR), %ebx
|
||||
leal L19, %esp
|
||||
jmp stackless_PCIConfig_Write
|
||||
L19:
|
||||
|
||||
/* Load the SideBand Packet Register to generate the transaction */
|
||||
movl $(PCI_CFG | HOST_BRIDGE_PFA | QNC_ACCESS_PORT_MCR), %ebx
|
||||
movb $QNC_MCR_BYTE_ENABLES, %cl /* Set all Byte Enable bits */
|
||||
xchgl %ecx, %eax
|
||||
leal L20, %esp
|
||||
jmp stackless_PCIConfig_Write
|
||||
L20:
|
||||
xchgl %ecx, %eax
|
||||
|
||||
movl %esi, %esp /* Restore the return address */
|
||||
RET32
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Procedure: stackless_PCIConfig_Write
|
||||
*
|
||||
* Input: esp - return address
|
||||
* eax - Data to write
|
||||
* ebx - PCI Config Address
|
||||
*
|
||||
* Output: None
|
||||
*
|
||||
* Destroys: dx
|
||||
*
|
||||
* Description:
|
||||
* Perform a DWORD PCI Configuration write
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
stackless_PCIConfig_Write:
|
||||
|
||||
/* Write the PCI Config Address to the address port */
|
||||
xchgl %ebx, %eax
|
||||
movw $(PCI_ADDRESS_PORT), %dx
|
||||
outl %eax, %dx
|
||||
xchgl %ebx, %eax
|
||||
|
||||
/* Write the PCI DWORD Data to the data port */
|
||||
movw $(PCI_DATA_PORT), %dx
|
||||
outl %eax, %dx
|
||||
|
||||
RET32
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------------
|
||||
*
|
||||
* Procedure: stackless_PCIConfig_Read
|
||||
*
|
||||
* Input: esp - return address
|
||||
* ebx - PCI Config Address
|
||||
*
|
||||
* Output: eax - Data read
|
||||
*
|
||||
* Destroys: eax
|
||||
* dx
|
||||
*
|
||||
* Description:
|
||||
* Perform a DWORD PCI Configuration read
|
||||
*
|
||||
*----------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
stackless_PCIConfig_Read:
|
||||
|
||||
/* Write the PCI Config Address to the address port */
|
||||
xchgl %ebx, %eax
|
||||
movw $(PCI_ADDRESS_PORT), %dx
|
||||
outl %eax, %dx
|
||||
xchgl %ebx, %eax
|
||||
|
||||
/* Read the PCI DWORD Data from the data port */
|
||||
movw $(PCI_DATA_PORT), %dx
|
||||
inl %dx, %eax
|
||||
|
||||
RET32
|
||||
|
||||
/*----------------------------------------------------------------------------*/
|
||||
|
||||
esram_init_done:
|
||||
|
||||
#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED)
|
||||
sd_led:
|
||||
|
||||
/* Set the SDIO controller's base address */
|
||||
movl $(SD_BASE_ADDR), %eax
|
||||
movl $(SD_CFG_ADDR), %ebx
|
||||
leal L40, %esp
|
||||
jmp stackless_PCIConfig_Write
|
||||
|
||||
L40:
|
||||
movl $(SD_CFG_ADDR), %ebx
|
||||
leal L41, %esp
|
||||
jmp stackless_PCIConfig_Read
|
||||
|
||||
L41:
|
||||
/* Enable the SDIO controller */
|
||||
movl $(SD_CFG_CMD), %ebx
|
||||
leal L42, %esp
|
||||
jmp stackless_PCIConfig_Read
|
||||
|
||||
L42:
|
||||
orl $2, %eax
|
||||
movl $(SD_CFG_CMD), %ebx
|
||||
leal L43, %esp
|
||||
jmp stackless_PCIConfig_Write
|
||||
|
||||
L43:
|
||||
movl $(SD_CFG_CMD), %ebx
|
||||
leal L44, %esp
|
||||
jmp stackless_PCIConfig_Read
|
||||
|
||||
L44:
|
||||
#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM)
|
||||
/* Turn on SD LED to indicate ESRAM successfully initialized */
|
||||
movl $SD_HOST_CTRL, %ebx
|
||||
movb 0(%ebx), %al
|
||||
orb $1, %al
|
||||
movb %al, 0(%ebx)
|
||||
|
||||
/* Loop forever */
|
||||
jmp .
|
||||
#endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */
|
||||
#endif /* CONFIG_ENABLE_DEBUG_LED */
|
||||
|
||||
/* Registers:
|
||||
* ebp: Low 32-bits of timestamp
|
||||
* edi: High 32-bits of timestamp
|
||||
*/
|
||||
|
||||
/* Setup bootblock stack */
|
||||
movl $_car_stack_end, %esp
|
||||
|
||||
before_carstage:
|
||||
post_code(0x2b)
|
||||
|
||||
/* Get the timestamp passed in bootblock_crt0.S */
|
||||
push %edi
|
||||
push %ebp
|
||||
|
||||
/* We can call into C functions now */
|
||||
call bootblock_main_with_timestamp
|
||||
|
||||
/* Never reached */
|
||||
Reference in New Issue
Block a user