soc/intel/quark: Add C bootblock

Add a bootblock which builds with C_ENVIRONMENT_BOOTBLOCK selected.
This is the first piece in supporting FSP 2.0.  Move esraminit from
romstage into the bootblock.  Replace cache_as_ram with
car_stage_entry.S and code in romstage.c

TEST=Build and run on Galileo Gen2

Change-Id: I14d2af2adb6e75d4bff1ebfb863196df04d07daf
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15132
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/quark/include/soc/romstage.h

@@ -25,6 +25,7 @@
 #include <fsp/romstage.h>
 #include <soc/reg_access.h>
 
+asmlinkage void *car_state_c_entry(void);
 uint32_t port_reg_read(uint8_t port, uint32_t offset);
 void port_reg_write(uint8_t port, uint32_t offset, uint32_t value);
 void report_platform_info(void);

src/soc/intel/quark/include/soc/sd.h

@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _QUARK_SD_H_
+#define _QUARK_SD_H_
+
+#define SD_PFA       (0x14 << 11)        /* B0:D20:F0 - SDIO controller */
+#define SD_CFG_BASE  (PCI_CFG | SD_PFA)  /* SD cntrl base in PCI config space */
+#define SD_CFG_CMD   (SD_CFG_BASE+0x04)  /* Command reg in PCI config space */
+#define SD_CFG_ADDR  (SD_CFG_BASE+0x10)  /* Base address in PCI config space */
+#define SD_BASE_ADDR (0xA0018000)        /* SD controller's base address */
+#define SD_HOST_CTRL (SD_BASE_ADDR+0x28) /* HOST_CTRL register */
+
+#endif /* _QUARK_SD_H_ */