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lib/fmap: Add optional pre-RAM cache

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This patch adds an optional pre-RAM cache for the FMAP which most
platforms should be able to use, complementing the recently added
post-RAM FMAP cache in CBMEM. vboot systems currently read the FMAP
about half a dozen times from flash in verstage, which will all be
coalesced into a single read with this patch. It will also help
future vboot improvements since when FMAP reads become "free" vboot
doesn't need to keep track of so much information separately.

In order to make sure we have a single, well-defined point where the new
cache is first initialized, eliminate the build-time hardcoding of the
CBFS section offsets, so that all CBFS accesses explicitly read the
FMAP.

Add FMAP_CACHEs to all platforms that can afford it (other than the
RISC-V things where I have no idea how they work), trying to take the
space from things that look like they were oversized anyway (pre-RAM
consoles and CBFS caches).

Change-Id: I2820436776ef620bdc4481b5cd4b6957764248ea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
This commit is contained in:
Julius Werner
2019-11-06 19:29:44 -08:00
parent 6abbd5b0ac
commit cefe89ee79
19 changed files with 132 additions and 68 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/soc/mediatek/mt8173/include/soc/memlayout.ld
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@@ -40,7 +40,8 @@ SECTIONS
SRAM_START(0x00100000)
VBOOT2_WORK(0x00100000, 12K)
VBOOT2_TPM_LOG(0x00103000, 2K)
PRERAM_CBMEM_CONSOLE(0x00103800, 14K)
FMAP_CACHE(0x00103800, 2K)
PRERAM_CBMEM_CONSOLE(0x00104000, 12K)
WATCHDOG_TOMBSTONE(0x00107000, 4)
PRERAM_CBFS_CACHE(0x00107004, 16K - 4)
TIMESTAMP(0x0010B000, 4K)

3
src/soc/mediatek/mt8183/include/soc/memlayout.ld
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@@ -34,7 +34,8 @@ SECTIONS
VBOOT2_TPM_LOG(0x00103000, 2K)
PRERAM_CBMEM_CONSOLE(0x00103800, 14K)
WATCHDOG_TOMBSTONE(0x00107000, 4)
PRERAM_CBFS_CACHE(0x00107004, 48K - 4)
PRERAM_CBFS_CACHE(0x00107004, 46K - 4)
FMAP_CACHE(0x00112800, 2K)
TIMESTAMP(0x00113000, 4K)
STACK(0x00114000, 16K)
TTB(0x00118000, 28K)

3
src/soc/nvidia/tegra124/include/soc/memlayout.ld
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@@ -28,7 +28,8 @@ SECTIONS
SRAM_START(0x40000000)
TTB(0x40000000, 16K + 32)
PRERAM_CBMEM_CONSOLE(0x40004020, 6K - 32)
PRERAM_CBFS_CACHE(0x40005800, 16K)
FMAP_CACHE(0x40005800, 2K)
PRERAM_CBFS_CACHE(0x40006000, 14K)
VBOOT2_WORK(0x40009800, 12K)
VBOOT2_TPM_LOG(0x4000D800, 2K)
STACK(0x4000E000, 8K)

3
src/soc/nvidia/tegra210/include/soc/memlayout.ld
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@@ -29,7 +29,8 @@ SECTIONS
{
SRAM_START(0x40000000)
PRERAM_CBMEM_CONSOLE(0x40000000, 2K)
PRERAM_CBFS_CACHE(0x40000800, 30K)
FMAP_CACHE(0x40000800, 2K)
PRERAM_CBFS_CACHE(0x40001000, 28K)
VBOOT2_WORK(0x40008000, 12K)
VBOOT2_TPM_LOG(0x4000B000, 2K)
#if ENV_ARM64

3
src/soc/qualcomm/ipq40xx/include/soc/memlayout.ld
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@@ -34,7 +34,8 @@ SECTIONS
/* This includes bootblock image, can be reused after bootblock starts */
/* UBER_SBL(0x0A0C0000, 48K) */
PRERAM_CBFS_CACHE(0x0A0C0000, 93K)
PRERAM_CBFS_CACHE(0x0A0C0000, 92K)
FMAP_CACHE(0x0A0EF800, 2K)
TTB(0x0A0F0000, 16K)
TTB_SUBTABLES(0x0A0F4000, 4K)

3
src/soc/qualcomm/ipq806x/include/soc/memlayout.ld
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@@ -38,7 +38,8 @@ SECTIONS
QCA_SHARED_RAM(2A03F000, 4K)
*/
STACK(0x2A040000, 16K)
PRERAM_CBFS_CACHE(0x2A044000, 93K)
PRERAM_CBFS_CACHE(0x2A044000, 91K)
FMAP_CACHE(0x2A05B000, 2K)
TTB_SUBTABLES(0x2A05B800, 2K)
TTB(0x2A05C000, 16K)
SRAM_END(0x2A060000)

3
src/soc/qualcomm/qcs405/include/soc/memlayout.ld
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@@ -39,7 +39,8 @@ SECTIONS
TIMESTAMP(0x8C4F000, 1K)
PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K)
PRERAM_CBFS_CACHE(0x8C57400, 70K)
REGION(bsram_unused, 0x8C68C00, 0xA2400, 0x100)
FMAP_CACHE(0x8C68C00, 2K)
REGION(bsram_unused, 0x8C69400, 0xA1C00, 0x100)
BSRAM_END(0x8D80000)
DRAM_START(0x80000000)

1
src/soc/qualcomm/sc7180/include/soc/memlayout.ld
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@@ -43,6 +43,7 @@ SECTIONS
REGION(ddr_training, 0x14850000, 8K, 4K)
REGION(qclib_serial_log, 0x14852000, 4K, 4K)
REGION(ddr_information, 0x14853000, 1K, 1K)
FMAP_CACHE(0x14853400, 2K)
REGION(dcb, 0x14870000, 16K, 4K)
REGION(pmic, 0x14874000, 44K, 4K)
REGION(limits_cfg, 0x1487F000, 4K, 4K)

3
src/soc/rockchip/rk3399/include/soc/memlayout.ld
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@@ -33,7 +33,8 @@ SECTIONS
#if ENV_RAMSTAGE
REGION(bl31_sram, 0xFF8C0000, 64K, 1)
#else
PRERAM_CBFS_CACHE(0xFF8C0000, 7K)
PRERAM_CBFS_CACHE(0xFF8C0000, 5K)
FMAP_CACHE(0xFF8C1400, 2K)
TIMESTAMP(0xFF8C1C00, 1K)
/* 0xFF8C2004 is the entry point address the masked ROM will jump to. */
OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4)

3
src/soc/samsung/exynos5250/include/soc/memlayout.ld
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@@ -31,7 +31,8 @@ SECTIONS
ROMSTAGE(0x2030000, 128K)
/* 32K hole */
TTB(0x2058000, 16K)
PRERAM_CBFS_CACHE(0x205C000, 78K)
PRERAM_CBFS_CACHE(0x205C000, 76K)
FMAP_CACHE(0x206F000, 2K)
VBOOT2_TPM_LOG(0x206F800, 2K)
VBOOT2_WORK(0x2070000, 12K)
STACK(0x2074000, 16K)

3
src/soc/samsung/exynos5420/include/soc/memlayout.ld
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@@ -32,7 +32,8 @@ SECTIONS
ROMSTAGE(0x2030000, 128K)
/* 32K hole */
TTB(0x2058000, 16K)
PRERAM_CBFS_CACHE(0x205C000, 76K)
PRERAM_CBFS_CACHE(0x205C000, 74K)
FMAP_CACHE(0x206E800, 2K)
STACK(0x206F000, 16K)
/* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't
* seem to be implemented right now? */