nb/intel/i945: Use common SMM_TSEG code

Use the common SMM_TSEG code to relocate the smihandler to TSEG.

This also caches the TSEG region and therefore increases MTRR usage a
little in some cases.

This fixes S3 resume being broken introduced by CB:25594
"sb/intel/i82801gx: Use common Intel SMM code".

Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.

Tested on Intel d945gclf and Lenovo Thinkpad X60.

Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25595
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/model_106cx/Makefile.inc

@@ -1,5 +1,6 @@
 ramstage-y += model_106cx_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../common
+subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
 
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin

src/cpu/intel/model_6ex/Makefile.inc

@@ -1,5 +1,6 @@
 ramstage-y += model_6ex_init.c
 subdirs-y += ../../x86/name
 subdirs-y += ../common
+subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
 
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin

src/cpu/intel/model_f3x/Makefile.inc

@@ -1,3 +1,4 @@
 ramstage-y += model_f3x_init.c
+subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
 
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f3x/microcode.bin

src/cpu/intel/model_f4x/Makefile.inc

@@ -1,3 +1,4 @@
 ramstage-y += model_f4x_init.c
+subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
 
 cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f4x/microcode.bin