sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/i945: Use common SMM_TSEG code

Browse Source 
Use the common SMM_TSEG code to relocate the smihandler to TSEG.

This also caches the TSEG region and therefore increases MTRR usage a
little in some cases.

This fixes S3 resume being broken introduced by CB:25594
"sb/intel/i82801gx: Use common Intel SMM code".

Currently SMRR msr's are not set on model_1067x and model_6fx since
this needs the MSRR enable bit and lock set in IA32_FEATURE_CONTROL.
This will be handled properly in the subsequent parallel mp init
patchset.

Tested on Intel d945gclf and Lenovo Thinkpad X60.

Change-Id: I0e6374746c3df96ce16f1c4a177af12747d6c1a9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/25595
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
2018-04-10 12:57:42 +02:00
parent 6af3e6f4ff
commit cf3076eff1
8 changed files with 55 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/southbridge/intel/i82801gx/Makefile.inc
View File

@@ -32,8 +32,10 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c
ramstage-y += watchdog.c
ifneq ($(CONFIG_SMM_TSEG),y)
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S
endif
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-y += early_smbus.c early_lpc.c