soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ

As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC
and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip).

ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip).

Change-Id: I7d223c165f819669722cbc80245fa8ec20372352
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/alderlake/Kconfig

@@ -139,10 +139,15 @@ config MAX_ROOT_PORTS
 	int
 	default MAX_PCH_ROOT_PORTS
 
-config MAX_PCIE_CLOCKS
+config MAX_PCIE_CLOCK_SRC
 	int
-	default 10 if SOC_INTEL_ALDERLAKE_PCH_M
-	default 12
+	default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+	default 7
+
+config MAX_PCIE_CLOCK_REQ
+	int
+	default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+	default 10
 
 config SMM_TSEG_SIZE
 	hex