sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ

Browse Source 
As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC
and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip).

ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip).

Change-Id: I7d223c165f819669722cbc80245fa8ec20372352
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2021-01-29 18:41:35 +05:30
committed by Patrick Georgi
parent 1cf2427d1d
commit cffc938934
3 changed files with 10 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/intel/alderlake/chip.h
View File

@@ -131,10 +131,10 @@ struct soc_intel_alderlake_config {
/* PCIe output clocks type to PCIe devices.
* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
* 0xFF: not used */
uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC];
/* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
* clksrc. */
uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_REQ];
/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS];