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soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ

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As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC
and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip).

ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip).

Change-Id: I7d223c165f819669722cbc80245fa8ec20372352
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2021-01-29 18:41:35 +05:30 committed by Patrick Georgi
parent 1cf2427d1d
commit cffc938934
3 changed files with 10 additions and 8 deletions
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3
src/mainboard/intel/adlrvp/devicetree.cb
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@ -84,9 +84,6 @@ chip soc/intel/alderlake
register "PchPcieRpEnable[2]" = "1" register "PchPcieRpEnable[2]" = "1"
register "PchPcieRpEnable[3]" = "1" register "PchPcieRpEnable[3]" = "1"
# Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below
register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED"
register "SataSalpSupport" = "1" register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{ register "SataPortsEnable" = "{

11
src/soc/intel/alderlake/Kconfig
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@ -139,10 +139,15 @@ config MAX_ROOT_PORTS
int int
default MAX_PCH_ROOT_PORTS default MAX_PCH_ROOT_PORTS
config MAX_PCIE_CLOCKS config MAX_PCIE_CLOCK_SRC
int int
default 10 if SOC_INTEL_ALDERLAKE_PCH_M default 6 if SOC_INTEL_ALDERLAKE_PCH_M
default 12 default 7
config MAX_PCIE_CLOCK_REQ
int
default 6 if SOC_INTEL_ALDERLAKE_PCH_M
default 10
config SMM_TSEG_SIZE config SMM_TSEG_SIZE
hex hex

4
src/soc/intel/alderlake/chip.h
View File

@ -131,10 +131,10 @@ struct soc_intel_alderlake_config {
/* PCIe output clocks type to PCIe devices. /* PCIe output clocks type to PCIe devices.
* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
* 0xFF: not used */ * 0xFF: not used */
uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC];
/* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
* clksrc. */ * clksrc. */
uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_REQ];
/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS]; uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS];