From d00cfcb0a1ec3669fdf3833cb3f2d11920bd622e Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 14 Feb 2022 12:55:31 +0100 Subject: [PATCH] nb/intel/ironlake/raminit_heci.c: Move to southbridge scope HECI stuff is in the southbridge, so put the code in there. Rename the file to match the name of the function it provides. Change-Id: I71de1234547dbd46a9b4959c619d2ae194da620a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/61931 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/ironlake/Makefile.inc | 1 - src/northbridge/intel/ironlake/raminit.h | 2 -- src/southbridge/intel/ibexpeak/Makefile.inc | 1 + src/southbridge/intel/ibexpeak/me.h | 2 ++ .../intel/ibexpeak/setup_heci_uma.c} | 2 +- 5 files changed, 4 insertions(+), 4 deletions(-) rename src/{northbridge/intel/ironlake/raminit_heci.c => southbridge/intel/ibexpeak/setup_heci_uma.c} (99%) diff --git a/src/northbridge/intel/ironlake/Makefile.inc b/src/northbridge/intel/ironlake/Makefile.inc index 126b6eb5f5..afca10c589 100644 --- a/src/northbridge/intel/ironlake/Makefile.inc +++ b/src/northbridge/intel/ironlake/Makefile.inc @@ -11,7 +11,6 @@ ramstage-y += gma.c romstage-y += memmap.c romstage-y += raminit.c -romstage-y += raminit_heci.c romstage-y += raminit_tables.c romstage-y += early_init.c romstage-y += romstage.c diff --git a/src/northbridge/intel/ironlake/raminit.h b/src/northbridge/intel/ironlake/raminit.h index 6dd07b3f24..edfce51125 100644 --- a/src/northbridge/intel/ironlake/raminit.h +++ b/src/northbridge/intel/ironlake/raminit.h @@ -106,6 +106,4 @@ u16 get_max_timing(struct raminfo *info, int channel); void early_quickpath_init(struct raminfo *info, const u8 x2ca8); void late_quickpath_init(struct raminfo *info, const int s3resume); -void setup_heci_uma(u64 heci_uma_addr, unsigned int heci_uma_size); - #endif /* RAMINIT_H */ diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index c8c96a8dfa..b33252fea4 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -33,6 +33,7 @@ romstage-y += early_thermal.c romstage-y += ../bd82x6x/early_rcba.c romstage-y += early_cir.c romstage-y += early_usb.c +romstage-y += setup_heci_uma.c CPPFLAGS_common += -I$(src)/southbridge/intel/ibexpeak/include diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h index 4eea0af2d5..8ff5ca7fa4 100644 --- a/src/southbridge/intel/ibexpeak/me.h +++ b/src/southbridge/intel/ibexpeak/me.h @@ -231,6 +231,8 @@ int intel_early_me_init(void); int intel_early_me_uma_size(void); int intel_early_me_init_done(u8 status); +void setup_heci_uma(u64 heci_uma_addr, unsigned int heci_uma_size); + typedef struct { u32 major_version : 16; u32 minor_version : 16; diff --git a/src/northbridge/intel/ironlake/raminit_heci.c b/src/southbridge/intel/ibexpeak/setup_heci_uma.c similarity index 99% rename from src/northbridge/intel/ironlake/raminit_heci.c rename to src/southbridge/intel/ibexpeak/setup_heci_uma.c index e54b05867c..70219e1adb 100644 --- a/src/northbridge/intel/ironlake/raminit_heci.c +++ b/src/southbridge/intel/ibexpeak/setup_heci_uma.c @@ -4,7 +4,7 @@ #include #include #include -#include +#include #include #include