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nb/intel/haswell: Drop gpu_panel_port_select

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The corresponding bits in PP_ON_DELAYS are reserved MBZ.

Change-Id: Icd2554c928a5908dfb354b81d3e6c5b5f242f1d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Angel Pons
2020-09-02 19:01:24 +02:00
committed by Patrick Georgi
parent f8d47455f7
commit d04957970c
7 changed files with 4 additions and 11 deletions
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3
src/mainboard/google/slippy/variants/falco/overridetree.cb
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@@ -1,7 +1,6 @@
chip northbridge/intel/haswell chip northbridge/intel/haswell
# Enable Panel and configure power delays # Set panel power delays
register "gpu_panel_port_select" = "1" # eDP
register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4) register "gpu_panel_power_cycle_delay" = "5" # 400ms (T4)
register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2) register "gpu_panel_power_up_delay" = "600" # 60ms (T1+T2)
register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7) register "gpu_panel_power_down_delay" = "600" # 60ms (T3+T7)

3
src/mainboard/google/slippy/variants/leon/overridetree.cb
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@@ -1,7 +1,6 @@
chip northbridge/intel/haswell chip northbridge/intel/haswell
# Enable Panel and configure power delays # Set panel power delays
register "gpu_panel_port_select" = "1" # eDP
register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_cycle_delay" = "5" # 400ms
register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_up_delay" = "400" # 40ms
register "gpu_panel_power_down_delay" = "150" # 15ms register "gpu_panel_power_down_delay" = "150" # 15ms

3
src/mainboard/google/slippy/variants/peppy/overridetree.cb
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@@ -1,7 +1,6 @@
chip northbridge/intel/haswell chip northbridge/intel/haswell
# Enable Panel and configure power delays # Set panel power delays
register "gpu_panel_port_select" = "1" # eDP
register "gpu_panel_power_cycle_delay" = "5" # 400ms register "gpu_panel_power_cycle_delay" = "5" # 400ms
register "gpu_panel_power_up_delay" = "400" # 40ms register "gpu_panel_power_up_delay" = "400" # 40ms
register "gpu_panel_power_down_delay" = "150" # 15ms register "gpu_panel_power_down_delay" = "150" # 15ms

3
src/mainboard/google/slippy/variants/wolf/overridetree.cb
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@@ -1,7 +1,6 @@
chip northbridge/intel/haswell chip northbridge/intel/haswell
# Enable Panel and configure power delays # Set panel power delays
register "gpu_panel_port_select" = "1" # eDP
register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12) register "gpu_panel_power_cycle_delay" = "6" # 500ms (T11+T12)
register "gpu_panel_power_up_delay" = "2000" # 200ms (T3) register "gpu_panel_power_up_delay" = "2000" # 200ms (T3)
register "gpu_panel_power_down_delay" = "500" # 50ms (T10) register "gpu_panel_power_down_delay" = "500" # 50ms (T10)

1
src/mainboard/lenovo/t440p/devicetree.cb
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@@ -4,7 +4,6 @@ chip northbridge/intel/haswell
register "gpu_dp_b_hotplug" = "4" register "gpu_dp_b_hotplug" = "4"
register "gpu_dp_c_hotplug" = "4" register "gpu_dp_c_hotplug" = "4"
register "gpu_dp_d_hotplug" = "4" register "gpu_dp_d_hotplug" = "4"
register "gpu_panel_port_select" = "0"
register "gpu_panel_power_backlight_off_delay" = "1" register "gpu_panel_power_backlight_off_delay" = "1"
register "gpu_panel_power_backlight_on_delay" = "1" register "gpu_panel_power_backlight_on_delay" = "1"
register "gpu_panel_power_cycle_delay" = "6" register "gpu_panel_power_cycle_delay" = "6"

1
src/northbridge/intel/haswell/chip.h
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@@ -17,7 +17,6 @@ struct northbridge_intel_haswell_config {
u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */ u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */ u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */
u8 gpu_panel_power_cycle_delay; /* T4 time sequence */ u8 gpu_panel_power_cycle_delay; /* T4 time sequence */
u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */
u16 gpu_panel_power_down_delay; /* T3 time sequence */ u16 gpu_panel_power_down_delay; /* T3 time sequence */

1
src/northbridge/intel/haswell/gma.c
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@@ -304,7 +304,6 @@ static void gma_setup_panel(struct device *dev)
/* Setup Panel Power On Delays */ /* Setup Panel Power On Delays */
reg32 = gtt_read(PCH_PP_ON_DELAYS); reg32 = gtt_read(PCH_PP_ON_DELAYS);
if (!reg32) { if (!reg32) {
reg32 = (conf->gpu_panel_port_select & 0x3) << 30;
reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16; reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16;
reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff);
gtt_write(PCH_PP_ON_DELAYS, reg32); gtt_write(PCH_PP_ON_DELAYS, reg32);