chip stuff

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@988 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/config/Config.lb

@@ -71,9 +71,9 @@ makerule linuxbios
 end
 
 makerule linuxbios.a   
-	depends	"$(OBJECTS-1)" 
+	depends	"$(OBJECTS)" 
 	action	"rm -f linuxbios.a"
-	action	"ar cr linuxbios.a $(OBJECTS-1)"
+	action	"ar cr linuxbios.a $(OBJECTS)"
 end
 
 #makerule crt0.S   
@@ -152,6 +152,7 @@ makerule clean
 	action	"rm -f TAGS tags"
 	action	"rm -f docipl"
 	action	"rm -f build_opt_tbl option_table.c crt0.S"
+	action	"rm -f chip_*.c"
 end
 
 # do standard config files that the user need not specify

src/devices/chip.c

@@ -0,0 +1,15 @@
+/* chips are arbitrary chips (superio, southbridge, etc.)
+ * They have private structures that define chip resources and default 
+ * settings. They have four externally visible functions for control. 
+ * They have a generic component which applies to all chips for 
+ * path, etc. 
+ */
+
+#include <device/chip.h>
+
+void
+chip_configure(struct chip *root, enum chip_pass pass)
+{
+	while (root) {
+	}
+}

src/include/device/chip.h

@@ -22,6 +22,14 @@ struct lpt_ports {
                      irq;    // irq
 };
 
+enum chip_pass {
+	CHIP_PRE_CONSOLE,
+	CHIP_PRE_DEVICE_ENUMERATE,
+	CHIP_PRE_DEVICE_CONFIGURE,
+	CHIP_PRE_DEVICE_ENABLE,
+	CHIP_PRE_DEVICE_INITIALIZE,
+	CHIP_PRE_BOOT
+};
 
 
 /* linkages from devices of a type (e.g. superio devices) 
@@ -33,10 +41,7 @@ struct chip;
 
 /* there is one of these for each TYPE of chip */
 struct chip_control {
-  void (*alloc)(struct chip *s);
-  void (*pre_pci_init)(struct chip *s);
-  void (*init)(struct chip *s);
-  void (*finishup)(struct chip *s);
+  void (*enable)(struct chip *, enum chip_pass);
   char *path;     /* the default path. Can be overridden
 		   * by commands in config
 		   */
@@ -54,3 +59,5 @@ struct chip {
   void *chip_info; /* the dreaded "void *" */
 };
 
+extern struct chip *root;
+extern void chip_configure(struct chip *, enum chip_pass);

src/superio/NSC/pc97307/chip.h

@@ -0,0 +1,5 @@
+
+struct superio_NSC_pc97307_config {
+    typedef struct com_ports com1;
+    typedef struct lpt_ports lpt;
+};

src/superio/NSC/pc97307/superio.c

@@ -2,6 +2,7 @@
 /* This code is distributed without warranty under the GPL v2 (see COPYING) */
 
 #include <arch/io.h>
+#include <device/chip.h>
 
 #ifndef PNP_INDEX_REG
 #define PNP_INDEX_REG	0x15C
@@ -18,26 +19,28 @@
 
 void pnp_output(char address, char data)
 {
-    outb(address, PNP_INDEX_REG);
-    outb(data, PNP_DATA_REG);
+	outb(address, PNP_INDEX_REG);
+	outb(data, PNP_DATA_REG);
 }
 
-void sio_enable(void)
+void sio_enable(struct chip *chip, enum chip_pass pass)
 {
-    /* Enable Super IO Chip */
-    pnp_output(0x07, 6); /* LD 6 = UART1 */
-    pnp_output(0x30, 0); /* Dectivate */
-    pnp_output(0x60, SIO_COM1_BASE >> 8); /* IO Base */
-    pnp_output(0x61, SIO_COM1_BASE & 0xFF); /* IO Base */
-    pnp_output(0x30, 1); /* Activate */
+	switch (pass) {
+	case CHIP_PRE_CONSOLE:
+		/* Enable Super IO Chip */
+		pnp_output(0x07, 6); /* LD 6 = UART1 */
+		pnp_output(0x30, 0); /* Dectivate */
+		pnp_output(0x60, chip->control->defaultport >> 8); /* IO Base */
+		pnp_output(0x61, chip->control->defaultport & 0xFF); /* IO Base */
+		pnp_output(0x30, 1); /* Activate */
+		break;
+	default:
+		/* nothing yet */
+	}
 }
 
-#if 0
 struct superio_control superio_NSC_pc97307_control = {
-	pre_pci_init:   (void *)0,
-	init:           (void *)0,
-	finishup:       (void *)0,
+	enable:   	sio_enable,
 	defaultport:    SIO_COM1_BASE,
 	name:           "NSC 87307"
 };
-#endif