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src/mb: Use system_reset()

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Use already defined system_reset() function.

Change-Id: I68ff4cffa2bfab6a15299795c3e1837fc9b85806
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Elyes HAOUAS
2019-04-21 20:17:11 +02:00
committed by Nico Huber
parent 363b77177e
commit d07048a7f9
10 changed files with 20 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/apple/macbook21/romstage.c
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@ -19,6 +19,7 @@
#include <stdint.h> #include <stdint.h>
#include <arch/io.h> #include <arch/io.h>
#include <cf9_reset.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
@ -245,8 +246,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, printk(BIOS_DEBUG,
"Soft reset detected, rebooting properly.\n"); "Soft reset detected, rebooting properly.\n");
outb(0x6, 0xcf9); system_reset();
halt();
} }
/* Perform some early chipset initialization required /* Perform some early chipset initialization required

4
src/mainboard/asus/p5gc-mx/romstage.c
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@ -19,6 +19,7 @@
#include <stdint.h> #include <stdint.h>
#include <arch/io.h> #include <arch/io.h>
#include <cf9_reset.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
@ -214,8 +215,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (!s3resume && setup_sio_gpio(c_bsel)) { if (!s3resume && setup_sio_gpio(c_bsel)) {
printk(BIOS_DEBUG, printk(BIOS_DEBUG,
"Needs reset to configure CPU BSEL straps\n"); "Needs reset to configure CPU BSEL straps\n");
outb(0xe, 0xcf9); full_reset();
halt();
} }
/* Enable SPD ROMs and DDR-II DRAM */ /* Enable SPD ROMs and DDR-II DRAM */

4
src/mainboard/asus/p5qpl-am/romstage.c
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@ -16,6 +16,7 @@
*/ */
#include <arch/io.h> #include <arch/io.h>
#include <cf9_reset.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h> #include <console/console.h>
@ -191,8 +192,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (!s3_resume && setup_sio_gpio()) { if (!s3_resume && setup_sio_gpio()) {
printk(BIOS_DEBUG, printk(BIOS_DEBUG,
"Needs reset to configure CPU BSEL straps\n"); "Needs reset to configure CPU BSEL straps\n");
outb(0xe, 0xcf9); full_reset();
halt();
} }
sdram_initialize(boot_path, spd_addrmap); sdram_initialize(boot_path, spd_addrmap);

4
src/mainboard/getac/p470/romstage.c
View File

@ -16,6 +16,7 @@
#include <stdint.h> #include <stdint.h>
#include <arch/io.h> #include <arch/io.h>
#include <cf9_reset.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
@ -256,8 +257,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
outb(0x6, 0xcf9); system_reset();
halt();
} }
/* Perform some early chipset initialization required /* Perform some early chipset initialization required

4
src/mainboard/ibase/mb899/romstage.c
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@ -18,6 +18,7 @@
#include <stdint.h> #include <stdint.h>
#include <halt.h> #include <halt.h>
#include <arch/io.h> #include <arch/io.h>
#include <cf9_reset.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <console/console.h> #include <console/console.h>
@ -218,8 +219,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
outb(0x6, 0xcf9); system_reset();
halt();
} }
/* Perform some early chipset initialization required /* Perform some early chipset initialization required

4
src/mainboard/intel/dcp847ske/early_southbridge.c
View File

@ -19,6 +19,7 @@
#include <stdint.h> #include <stdint.h>
#include <halt.h> #include <halt.h>
#include <arch/io.h> #include <arch/io.h>
#include <cf9_reset.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <console/console.h> #include <console/console.h>
@ -53,8 +54,7 @@ void mainboard_rcba_config(void)
RCBA32(BUC) &= ~PCH_DISABLE_GBE; RCBA32(BUC) &= ~PCH_DISABLE_GBE;
/* Datasheet says clearing the bit requires a reset after */ /* Datasheet says clearing the bit requires a reset after */
printk(BIOS_DEBUG, "Enabled gigabit ethernet, reset once.\n"); printk(BIOS_DEBUG, "Enabled gigabit ethernet, reset once.\n");
outb(0xe, 0xcf9); full_reset();
halt();
} }
#endif #endif

4
src/mainboard/kontron/986lcd-m/romstage.c
View File

@ -18,6 +18,7 @@
#include <stdint.h> #include <stdint.h>
#include <halt.h> #include <halt.h>
#include <arch/io.h> #include <arch/io.h>
#include <cf9_reset.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/intel/romstage.h> #include <cpu/intel/romstage.h>
#include <cpu/x86/bist.h> #include <cpu/x86/bist.h>
@ -266,8 +267,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
outb(0x6, 0xcf9); system_reset();
halt();
} }
/* Perform some early chipset initialization required /* Perform some early chipset initialization required

4
src/mainboard/lenovo/t60/romstage.c
View File

@ -19,6 +19,7 @@
#include <stdint.h> #include <stdint.h>
#include <arch/io.h> #include <arch/io.h>
#include <cf9_reset.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
@ -195,8 +196,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
outb(0x6, 0xcf9); system_reset();
halt();
} }
/* Perform some early chipset initialization required /* Perform some early chipset initialization required

4
src/mainboard/lenovo/z61t/romstage.c
View File

@ -19,6 +19,7 @@
#include <stdint.h> #include <stdint.h>
#include <arch/io.h> #include <arch/io.h>
#include <cf9_reset.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
@ -196,8 +197,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
outb(0x6, 0xcf9); system_reset();
halt();
} }
/* Perform some early chipset initialization required /* Perform some early chipset initialization required

4
src/mainboard/roda/rk886ex/romstage.c
View File

@ -18,6 +18,7 @@
#include <stdint.h> #include <stdint.h>
#include <arch/io.h> #include <arch/io.h>
#include <cf9_reset.h>
#include <device/pnp_ops.h> #include <device/pnp_ops.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
#include <device/pci_def.h> #include <device/pci_def.h>
@ -228,8 +229,7 @@ void mainboard_romstage_entry(unsigned long bist)
if (MCHBAR16(SSKPD) == 0xCAFE) { if (MCHBAR16(SSKPD) == 0xCAFE) {
printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
outb(0x6, 0xcf9); system_reset();
halt();
} }
/* Perform some early chipset initialization required /* Perform some early chipset initialization required