soc/amd/sabrina: Add espi_switch_to_spi1_pads

The way to select the pads has changed from Cezanne.

BUG=b:226635441
TEST=Build skyrim

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I96baf6b9c169ed61d221352b29ac676bca40da21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63095
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/sabrina/Makefile.inc

@@ -12,6 +12,7 @@ all-y		+= aoac.c
 
 bootblock-y	+= bootblock.c
 bootblock-y	+= early_fch.c
+bootblock-y	+= espi_util.c
 bootblock-y	+= gpio.c
 bootblock-y	+= i2c.c
 bootblock-y	+= reset.c

src/soc/amd/sabrina/espi_util.c

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/spi.h>
+#include <soc/espi.h>
+#include <types.h>
+
+#define ESPI_CNTRL_REGISTER	0x10
+#define  LOCK_SPIX10_BIT2	BIT(3)
+#define  ESPI_MUX_SPI1		BIT(2)
+#define  ROM_ADDR_WR_PROT	BIT(1)
+#define  DIS_ESPI_MASCTL_REG_WR	BIT(0)
+
+void espi_switch_to_spi1_pads(void)
+{
+	uint8_t reg = spi_read8(ESPI_CNTRL_REGISTER);
+
+	reg |= ESPI_MUX_SPI1;
+
+	spi_write8(ESPI_CNTRL_REGISTER, reg);
+}

src/soc/amd/sabrina/include/soc/espi.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_SABRINA_ESPI_H
+#define AMD_SABRINA_ESPI_H
+
+void espi_switch_to_spi1_pads(void);
+
+#endif /* AMD_SABRINA_ESPI_H */