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Supermicro H8QME-2+ (Fam10) whitespace fixes (trivial).

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This makes the code more similar to the h8dmr_fam10 target in order to make
the diff between both smaller and more readable.

Build-tested with newconfig and kconfig.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-02-03 22:07:57 +00:00
parent 3fb8c6637e
commit d0d7c0158d
8 changed files with 83 additions and 105 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
src/mainboard/supermicro/h8qme_fam10/Config.lb
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@ -288,12 +288,12 @@ chip northbridge/amd/amdfam10/root_complex
device pci 5.0 on end # SATA 0 device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.1 off end # AZA device pci 6.1 off end # AZA
device pci 7.0 on device pci 7.0 on
device pci 1.0 on end device pci 1.0 on end
end end
device pci 8.0 off end device pci 8.0 off end
device pci 9.0 off end device pci 9.0 off end
device pci a.0 on end # PCI E 5 device pci a.0 on end # PCI E 5
device pci b.0 on end # PCI E 4 device pci b.0 on end # PCI E 4
device pci c.0 on end # PCI E 3 device pci c.0 on end # PCI E 3
@ -312,20 +312,18 @@ chip northbridge/amd/amdfam10/root_complex
device pci 18.3 on end device pci 18.3 on end
device pci 18.4 on end device pci 18.4 on end
device pci 19.0 on end device pci 19.0 on end
device pci 19.0 on end device pci 19.0 on end
device pci 19.0 on device pci 19.0 on
chip southbridge/amd/amd8132 chip southbridge/amd/amd8132
device pci 0.0 on end device pci 0.0 on end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on device pci 1.0 on
device pci 3.0 on end device pci 3.0 on end
device pci 3.1 on end device pci 3.1 on end
end end
device pci 1.1 on end device pci 1.1 on end
end #amd8132
end #amd8132 end #device pci 19.0
end #device pci 19.0
device pci 19.1 on end device pci 19.1 on end
device pci 19.2 on end device pci 19.2 on end
device pci 19.3 on end device pci 19.3 on end

11
src/mainboard/supermicro/h8qme_fam10/Options.lb
View File

@ -141,6 +141,7 @@ default CONFIG_FAILOVER_SIZE=0x02000
#more 1M for pgtbl #more 1M for pgtbl
default CONFIG_RAMTOP=16384*1024 default CONFIG_RAMTOP=16384*1024
#default CONFIG_RAMTOP=16384*8192 #default CONFIG_RAMTOP=16384*8192
## ##
## Build code for the fallback boot ## Build code for the fallback boot
## ##
@ -162,7 +163,6 @@ default CONFIG_IRQ_SLOT_COUNT=11
## Build code to export an x86 MP table ## Build code to export an x86 MP table
## Useful for specifying IRQ routing values ## Useful for specifying IRQ routing values
## ##
##default CONFIG_GENERATE_MP_TABLE=1
default CONFIG_GENERATE_MP_TABLE=1 default CONFIG_GENERATE_MP_TABLE=1
## ACPI tables will be included ## ACPI tables will be included
@ -272,10 +272,15 @@ default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_0100009f.h"
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 0x1e000 default CONFIG_ROM_IMAGE_SIZE = 0x1e000
##
## Use a 64K stack
##
default CONFIG_STACK_SIZE=0x10000 default CONFIG_STACK_SIZE=0x10000
default CONFIG_HEAP_SIZE= 0xc000
##
## Use a 48K heap
##
default CONFIG_HEAP_SIZE=0xc000
## ##
## Only use the option table in a normal image ## Only use the option table in a normal image

7
src/mainboard/supermicro/h8qme_fam10/apc_auto.c
View File

@ -64,32 +64,25 @@ static void post_code(uint8_t value) {
#endif #endif
#include <cpu/amd/model_fxx_rev.h> #include <cpu/amd/model_fxx_rev.h>
//#include "northbridge/amd/amdk8/raminit.h"
#include "northbridge/amd/amkfam10/raminit.h" #include "northbridge/amd/amkfam10/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c" #include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c" #include "lib/delay.c"
//#include "cpu/x86/lapic/boot_cpu.c" //#include "cpu/x86/lapic/boot_cpu.c"
//#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdfam10/reset_test.c" #include "northbridge/amd/amdfam10/reset_test.c"
//#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/debug.c"
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
//#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdfam10/amdfam10.h" #include "northbridge/amd/amdfam10/amdfam10.h"
#include "cpu/x86/mtrr.h" #include "cpu/x86/mtrr.h"
#include "cpu/amd/mtrr.h" #include "cpu/amd/mtrr.h"
#include "cpu/x86/tsc.h" #include "cpu/x86/tsc.h"
//#include "northbridge/amd/amdk8/amdk8_f_pci.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "northbridge/amd/amdk8/raminit_f_dqs.c" #include "northbridge/amd/amdk8/raminit_f_dqs.c"

20
src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
View File

@ -64,7 +64,6 @@ static unsigned hcdnx[] = {
unsigned sbdn3; unsigned sbdn3;
extern void get_pci1234(void); extern void get_pci1234(void);
static unsigned get_bus_conf_done = 0; static unsigned get_bus_conf_done = 0;
@ -99,9 +98,8 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff; m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
m->bus_8132_0 = (sysconf.pci1234[1] >> 12) & 0xff;
m->bus_8132_0 = (sysconf.pci1234[1] >> 12) & 0xff; sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain
sbdn3 =(sysconf.hcdn[1] & 0xff); // first byte of second chain
/* MCP55 */ /* MCP55 */
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0)); dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
@ -123,21 +121,21 @@ void get_bus_conf(void)
} }
} }
/*8132_1*/ /* 8132_1 */
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3,0)); dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3, 0));
m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
m->bus_8132_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_8132_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
m->bus_8132_2++; m->bus_8132_2++;
/*8132_2*/
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3+1,0)); /* 8132_2 */
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3 + 1, 0));
m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
m->bus_isa++; m->bus_isa++;
for(i=0; i< sysconf.hc_possible_num; i++) { for(i=0; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff; unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff;
@ -155,6 +153,6 @@ void get_bus_conf(void)
apicid_base = CONFIG_MAX_PHYSICAL_CPUS; apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif #endif
m->apicid_mcp55 = apicid_base+0; m->apicid_mcp55 = apicid_base+0;
m->apicid_8132_1 = apicid_base+1; m->apicid_8132_1 = apicid_base+1;
m->apicid_8132_2 = apicid_base+2; m->apicid_8132_2 = apicid_base+2;
} }

2
src/mainboard/supermicro/h8qme_fam10/mainboard.c
View File

@ -27,5 +27,5 @@
#include "chip.h" #include "chip.h"
struct chip_operations mainboard_ops = { struct chip_operations mainboard_ops = {
CHIP_NAME("Supermicro H8QME Mainboard (Family 10)") CHIP_NAME("Supermicro H8QME-2+ Mainboard (Family 10)")
}; };

11
src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h
View File

@ -28,12 +28,11 @@ struct mb_sysconf_t {
unsigned apicid_mcp55; unsigned apicid_mcp55;
unsigned bus_type[256]; unsigned bus_type[256];
unsigned char bus_8132_0; //7 unsigned char bus_8132_0; //7
unsigned char bus_8132_1; //8 unsigned char bus_8132_1; //8
unsigned char bus_8132_2; //9 unsigned char bus_8132_2; //9
unsigned apicid_8132_1; unsigned apicid_8132_1;
unsigned apicid_8132_2; unsigned apicid_8132_2;
}; };
#endif #endif

83
src/mainboard/supermicro/h8qme_fam10/mptable.c
View File

@ -41,7 +41,6 @@ void *smp_write_config_table(void *v)
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
unsigned sbdn; unsigned sbdn;
int i,j; int i,j;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -67,8 +66,6 @@ void *smp_write_config_table(void *v)
sbdn = sysconf.sbdn; sbdn = sysconf.sbdn;
m = sysconf.mb; m = sysconf.mb;
/*Bus: Bus ID Type*/ /*Bus: Bus ID Type*/
/* define bus and isa numbers */ /* define bus and isa numbers */
for(j= 0; j < 256 ; j++) { for(j= 0; j < 256 ; j++) {
@ -77,22 +74,13 @@ void *smp_write_config_table(void *v)
} }
smp_write_bus(mc, m->bus_isa, "ISA "); smp_write_bus(mc, m->bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;
uint32_t dword; uint32_t dword;
//void smp_write_ioapic(struct mp_config_table *mc, unsigned char id, unsigned char ver, unsigned long apicaddr);
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1); res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) { if (res) {
@ -103,7 +91,7 @@ void *smp_write_config_table(void *v)
pci_write_config32(dev, 0x7c, dword); pci_write_config32(dev, 0x7c, dword);
dword = 0x5ab0a500; dword = 0x5ab0a500;
pci_write_config32(dev, 0x80, dword); pci_write_config32(dev, 0x80, dword);
dword = 0xa000000b; dword = 0xa000000b;
dword = 0x10000002; dword = 0x10000002;
@ -111,47 +99,44 @@ void *smp_write_config_table(void *v)
} }
/* 8132_1*/ /* 8132_1 */
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3,1)); dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3,1));
res = find_resource(dev,PCI_BASE_ADDRESS_0); res = find_resource(dev,PCI_BASE_ADDRESS_0);
smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base); smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
/* 8132_2*/ /* 8132_2 */
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3+1,1)); dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3+1,1));
res = find_resource(dev,PCI_BASE_ADDRESS_0); res = find_resource(dev,PCI_BASE_ADDRESS_0);
smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base); smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
}
} /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_mcp55, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_mcp55, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_mcp55, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_mcp55, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_mcp55, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_mcp55, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_mcp55, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus! Not correctly assign!!*/
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0xb); /* 11 USB, OK */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0xa); /* 10 USB, OK */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x5); /* 5 IDE, OK*/
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID * PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_mcp55, 0x3);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_mcp55, 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_mcp55, 0x6);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_mcp55, 0x7);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_mcp55, 0x8);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_mcp55, 0xc);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_mcp55, 0xd);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus! Not correctly assign!!*/ for(j=7;j>=2; j--) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0xb); /* 11 USB, OK */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0xa); /* 10 USB, OK */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x5); /* 5 IDE, OK*/
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0xa); /* 10 IDE, OK*/
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+6)<<2)|1, m->apicid_mcp55, 0xa); /* 10 VGA, OK*/
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/
for(j=7;j>=2; j--) {
if(!m->bus_mcp55[j]) continue; if(!m->bus_mcp55[j]) continue;
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
@ -172,7 +157,7 @@ for(j=7;j>=2; j--) {
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
printk_debug("Wrote the mp table end at: %p - %p\n", printk_debug("Wrote the mp table end at: %p - %p\n",
mc, smp_next_mpe_entry(mc)); mc, smp_next_mpe_entry(mc));
return smp_next_mpe_entry(mc); return smp_next_mpe_entry(mc);
} }

6
src/mainboard/supermicro/h8qme_fam10/spd_addr.h
View File

@ -107,9 +107,9 @@ static const u8 spd_addr[] = {
RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0,
#endif #endif
#if CONFIG_MAX_PHYSICAL_CPUS > 2 #if CONFIG_MAX_PHYSICAL_CPUS > 2
// third node //third node
RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
// forth node //forth node
RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0, RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0,
#endif #endif
}; };