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Supermicro H8QME-2+ (Fam10) whitespace fixes (trivial).

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This makes the code more similar to the h8dmr_fam10 target in order to make
the diff between both smaller and more readable.

Build-tested with newconfig and kconfig.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2010-02-03 22:07:57 +00:00
parent 3fb8c6637e
commit d0d7c0158d
8 changed files with 83 additions and 105 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/supermicro/h8qme_fam10/Config.lb
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@ -322,9 +322,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 3.1 on end
end
device pci 1.1 on end
end #amd8132
end #device pci 19.0
device pci 19.1 on end
device pci 19.2 on end

11
src/mainboard/supermicro/h8qme_fam10/Options.lb
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@ -141,6 +141,7 @@ default CONFIG_FAILOVER_SIZE=0x02000
#more 1M for pgtbl
default CONFIG_RAMTOP=16384*1024
#default CONFIG_RAMTOP=16384*8192
##
## Build code for the fallback boot
##
@ -162,7 +163,6 @@ default CONFIG_IRQ_SLOT_COUNT=11
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
##default CONFIG_GENERATE_MP_TABLE=1
default CONFIG_GENERATE_MP_TABLE=1
## ACPI tables will be included
@ -272,10 +272,15 @@ default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_0100009f.h"
## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
default CONFIG_ROM_IMAGE_SIZE = 0x1e000
##
## Use a 64K stack
##
default CONFIG_STACK_SIZE=0x10000
default CONFIG_HEAP_SIZE= 0xc000
##
## Use a 48K heap
##
default CONFIG_HEAP_SIZE=0xc000
##
## Only use the option table in a normal image

7
src/mainboard/supermicro/h8qme_fam10/apc_auto.c
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@ -64,32 +64,25 @@ static void post_code(uint8_t value) {
#endif
#include <cpu/amd/model_fxx_rev.h>
//#include "northbridge/amd/amdk8/raminit.h"
#include "northbridge/amd/amkfam10/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
//#include "cpu/x86/lapic/boot_cpu.c"
//#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdfam10/reset_test.c"
//#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdfam10/debug.c"
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
//#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "cpu/x86/mtrr.h"
#include "cpu/amd/mtrr.h"
#include "cpu/x86/tsc.h"
//#include "northbridge/amd/amdk8/amdk8_f_pci.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
#include "northbridge/amd/amdk8/raminit_f_dqs.c"

4
src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
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@ -64,7 +64,6 @@ static unsigned hcdnx[] = {
unsigned sbdn3;
extern void get_pci1234(void);
static unsigned get_bus_conf_done = 0;
@ -99,7 +98,6 @@ void get_bus_conf(void)
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
m->bus_8132_0 = (sysconf.pci1234[1] >> 12) & 0xff;
sbdn3 = (sysconf.hcdn[1] & 0xff); // first byte of second chain
@ -129,8 +127,8 @@ void get_bus_conf(void)
m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
m->bus_8132_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
m->bus_8132_2++;
/*8132_2*/
/* 8132_2 */
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3 + 1, 0));
m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);

2
src/mainboard/supermicro/h8qme_fam10/mainboard.c
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@ -27,5 +27,5 @@
#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Supermicro H8QME Mainboard (Family 10)")
CHIP_NAME("Supermicro H8QME-2+ Mainboard (Family 10)")
};

1
src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h
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@ -33,7 +33,6 @@ unsigned char bus_8132_1; //8
unsigned char bus_8132_2; //9
unsigned apicid_8132_1;
unsigned apicid_8132_2;
};
#endif

17
src/mainboard/supermicro/h8qme_fam10/mptable.c
View File

@ -41,7 +41,6 @@ void *smp_write_config_table(void *v)
struct mb_sysconf_t *m;
unsigned sbdn;
int i,j;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@ -67,8 +66,6 @@ void *smp_write_config_table(void *v)
sbdn = sysconf.sbdn;
m = sysconf.mb;
/*Bus: Bus ID Type*/
/* define bus and isa numbers */
for(j= 0; j < 256 ; j++) {
@ -77,22 +74,13 @@ void *smp_write_config_table(void *v)
}
smp_write_bus(mc, m->bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
uint32_t dword;
//void smp_write_ioapic(struct mp_config_table *mc, unsigned char id, unsigned char ver, unsigned long apicaddr);
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) {
@ -121,11 +109,9 @@ void *smp_write_config_table(void *v)
res = find_resource(dev,PCI_BASE_ADDRESS_0);
smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
}
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID * PIN# */
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_mcp55, 0x1);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_mcp55, 0x2);
@ -150,7 +136,6 @@ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mc
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|0, m->apicid_mcp55, 0x5); /* 5 eth0, OK*/
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, ((3)<<2)|1, m->apicid_mcp55, 0xb); /* 11 eth1, OK*/
for(j=7;j>=2; j--) {
if(!m->bus_mcp55[j]) continue;
for(i=0;i<4;i++) {