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Fixes for S0ix

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Change-Id: I293b4219332f6ea58f81a231a613b03b74f5e1c4
This commit is contained in:
Jeremy Soller
2020-12-22 14:28:06 -07:00
parent 7e69c5aae8
commit d0dbaebd28
1 changed files with 8 additions and 7 deletions
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15
src/mainboard/system76/darp7/devicetree.cb
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@@ -285,12 +285,13 @@ chip soc/intel/tigerlake
register "PcieRpLtrEnable[5]" = "1" register "PcieRpLtrEnable[5]" = "1"
register "PcieClkSrcUsage[2]" = "5" register "PcieClkSrcUsage[2]" = "5"
register "PcieClkSrcClkReq[2]" = "2" register "PcieClkSrcClkReq[2]" = "2"
chip soc/intel/common/block/pcie/rtd3 #TODO: fix suspend/resume failure
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U4)" # GPIO_SDCARD_EN # chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D2)" # GPP_D2_SDCARD_RST# # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U4)" # GPIO_SDCARD_EN
register "srcclk_pin" = "2" # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D2)" # GPP_D2_SDCARD_RST#
device generic 0 on end # register "srcclk_pin" = "2"
end # device generic 0 on end
# end
end end
device ref pcie_rp7 on device ref pcie_rp7 on
# PCIe root port #7 x1, Clock 3 (GLAN) # PCIe root port #7 x1, Clock 3 (GLAN)
@@ -301,7 +302,7 @@ chip soc/intel/tigerlake
chip soc/intel/common/block/pcie/rtd3 chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN
#TODO: should this be GPIO_LANRTD3 or LAN_PLT_RST# ? #TODO: should this be GPIO_LANRTD3 or LAN_PLT_RST# ?
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # LAN_PLT_RST# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # GPIO_LANRTD3
register "srcclk_pin" = "3" # GLAN_CLKREQ# register "srcclk_pin" = "3" # GLAN_CLKREQ#
device generic 0 on end device generic 0 on end
end end