intel/skylake: IRQ programming through UPD
Implemented Device IRQ porgramming, PxRC to IRQ mapping, GPIO IRQ routing, SCI IRQ select through UPD BUG=NONE BRANCH=NONE CQ-DEPEND=CL:*232948 TEST= build and booted sklrvp,kunimitsu with this changes. Change-Id: Ic98074491fe5251a48ed55b6fb7ef31809c3abf3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 534bd65e5df8654d745c8efe491a332336c9cdc3 Original-Change-Id: I4ea6f3cdb15d371c6023bfd046f3475290f5aa26 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291403 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12146 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Subrata Banik
committed by
Patrick Georgi
Patrick Georgi
parent
9cd8e5aebf
commit
d0def39413
@@ -24,10 +24,207 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <fsp/util.h>
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#include <soc/interrupt.h>
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#include <soc/irq.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <string.h>
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static const SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = {
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/*
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* cAVS(Audio, Voice, Speach), INTA is default, programmed in
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* PciCfgSpace 3Dh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC,
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PCI_FUNC(PCH_DEVFN_HDA), int_A, cAVS_INTA_IRQ),
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/*
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* SMBus Controller, no default value, programmed in
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* PciCfgSpace 3Dh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC,
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PCI_FUNC(PCH_DEVFN_SMBUS), int_A, SMBUS_INTA_IRQ),
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/* GbE Controller, INTA is default, programmed in PciCfgSpace 3Dh */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC,
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PCI_FUNC(PCH_DEVFN_GBE), int_A, GbE_INTA_IRQ),
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/* TraceHub, INTA is default, RO register */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_LPC,
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PCI_FUNC(PCH_DEVFN_TRACEHUB), int_A, TRACE_HUB_INTA_IRQ),
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/*
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* SerialIo: UART #0, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[7]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
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PCI_FUNC(PCH_DEVFN_UART0), int_A, LPSS_UART0_IRQ),
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/*
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* SerialIo: UART #1, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[8]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
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PCI_FUNC(PCH_DEVFN_UART1), int_B, LPSS_UART1_IRQ),
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/*
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* SerialIo: SPI #0, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[10]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
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PCI_FUNC(PCH_DEVFN_GSPI0), int_C, LPSS_SPI0_IRQ),
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/*
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* SerialIo: SPI #1, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[11]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
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PCI_FUNC(PCH_DEVFN_GSPI1), int_D, LPSS_SPI1_IRQ),
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/* SCS: eMMC (SKL PCH-LP Only) */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
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PCI_FUNC(PCH_DEVFN_EMMC), int_B, eMMC_IRQ),
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/* SCS: SDIO (SKL PCH-LP Only) */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
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PCI_FUNC(PCH_DEVFN_SDIO), int_C, SDIO_IRQ),
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/* SCS: SDCard (SKL PCH-LP Only) */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_STORAGE,
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PCI_FUNC(PCH_DEVFN_SDCARD), int_D, SD_IRQ),
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/* PCI Express Port 9, INT is default, programmed in PciCfgSpace + FCh */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1,
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PCI_FUNC(PCH_DEVFN_PCIE9), int_A, PCIE_9_IRQ),
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/* PCI Express Port 10, INT is default, programmed in PciCfgSpace + FCh */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1,
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PCI_FUNC(PCH_DEVFN_PCIE10), int_B, PCIE_10_IRQ),
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/* PCI Express Port 11, INT is default, programmed in PciCfgSpace + FCh */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1,
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PCI_FUNC(PCH_DEVFN_PCIE11), int_C, PCIE_11_IRQ),
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/* PCI Express Port 12, INT is default, programmed in PciCfgSpace + FCh */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE_1,
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PCI_FUNC(PCH_DEVFN_PCIE12), int_D, PCIE_12_IRQ),
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/*
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* PCI Express Port 1, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
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PCI_FUNC(PCH_DEVFN_PCIE1), int_A, PCIE_1_IRQ),
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/*
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* PCI Express Port 2, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
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PCI_FUNC(PCH_DEVFN_PCIE2), int_B, PCIE_2_IRQ),
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/*
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* PCI Express Port 3, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
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PCI_FUNC(PCH_DEVFN_PCIE3), int_C, PCIE_3_IRQ),
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/*
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* PCI Express Port 4, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
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PCI_FUNC(PCH_DEVFN_PCIE4), int_D, PCIE_4_IRQ),
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/*
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* PCI Express Port 5, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
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PCI_FUNC(PCH_DEVFN_PCIE5), int_A, PCIE_5_IRQ),
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/*
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* PCI Express Port 6, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
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PCI_FUNC(PCH_DEVFN_PCIE6), int_B, PCIE_6_IRQ),
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/*
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* PCI Express Port 7, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
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PCI_FUNC(PCH_DEVFN_PCIE7), int_C, PCIE_7_IRQ),
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/*
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* PCI Express Port 8, INT is default,
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* programmed in PciCfgSpace + FCh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_PCIE,
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PCI_FUNC(PCH_DEVFN_PCIE8), int_D, PCIE_8_IRQ),
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/*
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* SerialIo UART Controller #2, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[9]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2,
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PCI_FUNC(PCH_DEVFN_UART2), int_A, LPSS_UART2_IRQ),
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/*
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* SerialIo UART Controller #5, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[6]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2,
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PCI_FUNC(PCH_DEVFN_I2C5), int_B, LPSS_I2C5_IRQ),
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/*
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* SerialIo UART Controller #4, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[5]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO2,
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PCI_FUNC(PCH_DEVFN_I2C4), int_C, LPSS_I2C4_IRQ),
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/*
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* SATA Controller, INTA is default,
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* programmed in PciCfgSpace + 3Dh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA,
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PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ),
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/* CSME: HECI #1 */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME,
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PCI_FUNC(PCH_DEVFN_ME), int_A, HECI_1_IRQ),
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/* CSME: HECI #2 */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME,
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PCI_FUNC(PCH_DEVFN_ME_2), int_B, HECI_2_IRQ),
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/* CSME: IDE-Redirection (IDE-R) */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME,
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PCI_FUNC(PCH_DEVFN_ME_IDER), int_C, IDER_IRQ),
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/* CSME: Keyboard and Text (KT) Redirection */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME,
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PCI_FUNC(PCH_DEVFN_ME_KT), int_D, KT_IRQ),
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/* CSME: HECI #3 */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME,
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PCI_FUNC(PCH_DEVFN_ME_3), int_A, HECI_3_IRQ),
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/*
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* SerialIo I2C Controller #0, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[1]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1,
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PCI_FUNC(PCH_DEVFN_I2C0), int_A, LPSS_I2C0_IRQ),
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/*
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* SerialIo I2C Controller #1, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[2]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1,
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PCI_FUNC(PCH_DEVFN_I2C1), int_B, LPSS_I2C1_IRQ),
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/*
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* SerialIo I2C Controller #2, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[3]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1,
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PCI_FUNC(PCH_DEVFN_I2C2), int_C, LPSS_I2C2_IRQ),
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/*
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* SerialIo I2C Controller #3, INTA is default,
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* programmed in PCR[SERIALIO] + PCICFGCTRL[4]
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_SIO1,
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PCI_FUNC(PCH_DEVFN_I2C3), int_D, LPSS_I2C3_IRQ),
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/*
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* USB 3.0 xHCI Controller, no default value,
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* programmed in PciCfgSpace 3Dh
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*/
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI,
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PCI_FUNC(PCH_DEVFN_XHCI), int_A, XHCI_IRQ),
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/* USB Device Controller (OTG) */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI,
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PCI_FUNC(PCH_DEVFN_USBOTG), int_B, OTG_IRQ),
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/* Thermal Subsystem */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI,
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PCI_FUNC(PCH_DEVFN_THERMAL), int_C, THRMAL_IRQ),
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/* Camera IO Host Controller */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_XHCI,
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PCI_FUNC(PCH_DEVFN_CIO), int_A, CIO_INTA_IRQ),
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/* Integrated Sensor Hub */
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DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH,
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PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ)
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};
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static void pci_domain_set_resources(device_t dev)
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{
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assign_resources(dev->link_list);
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@@ -72,6 +269,9 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
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{
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const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
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const struct soc_intel_skylake_config *config = dev->chip_info;
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u8 irq_config[PCH_MAX_IRQ_CONFIG];
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int i;
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int intdeventry;
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memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
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sizeof(params->SerialIoDevMode));
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@@ -118,6 +318,49 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
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/* Show SPI controller if enabled in devicetree.cb */
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dev = dev_find_slot(0, PCH_DEVFN_SPI);
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params->ShowSpiController = dev->enabled;
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/* Get Device Int Count */
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intdeventry = ARRAY_SIZE(devintconfig);
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/*update irq table*/
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memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *)(params->DevIntConfigPtr), devintconfig,
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intdeventry * sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG));
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params->NumOfDevIntConfig = intdeventry;
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/* PxRC to IRQ programing */
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for (i = 0; i < PCH_MAX_IRQ_CONFIG; i++) {
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switch(i) {
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case PCH_PARC:
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case PCH_PCRC:
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case PCH_PDRC:
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case PCH_PERC:
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case PCH_PFRC:
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case PCH_PGRC:
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case PCH_PHRC:
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irq_config[i] = PCH_IRQ11;
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break;
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case PCH_PBRC:
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irq_config[PCH_PBRC] = PCH_IRQ10;
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break;
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}
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}
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memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG);
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/* GPIO IRQ Route The valid values is 14 or 15*/
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if(config->GpioIrqSelect == 0)
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params->GpioIrqRoute = GPIO_IRQ14;
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else
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params->GpioIrqRoute = config->GpioIrqSelect;
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/* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23*/
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if(config->SciIrqSelect == 0)
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params->SciIrqSelect = SCI_IRQ9;
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else
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params->SciIrqSelect = config->SciIrqSelect;
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/* TCO IRQ Select The valid values is 9, 10, 11, 20 21, 22, 23*/
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if(config->TcoIrqSelect == 0)
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params->TcoIrqSelect = TCO_IRQ9;
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else
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params->TcoIrqSelect = config->TcoIrqSelect;
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/* TCO Irq enable/disable */
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params->TcoIrqEnable = config->TcoIrqEnable;
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}
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void soc_display_silicon_init_params(const SILICON_INIT_UPD *original,
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@@ -286,6 +529,45 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original,
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params->EnableSata);
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soc_display_upd_value("SataMode", 1, original->SataMode,
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params->SataMode);
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soc_display_upd_value("NumOfDevIntConfig", 1,
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original->NumOfDevIntConfig,
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params->NumOfDevIntConfig);
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soc_display_upd_value("PxRcConfig[PARC]", 1,
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original->PxRcConfig[PCH_PARC],
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params->PxRcConfig[PCH_PARC]);
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soc_display_upd_value("PxRcConfig[PBRC]", 1,
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original->PxRcConfig[PCH_PBRC],
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params->PxRcConfig[PCH_PBRC]);
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soc_display_upd_value("PxRcConfig[PCRC]", 1,
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original->PxRcConfig[PCH_PCRC],
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params->PxRcConfig[PCH_PCRC]);
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soc_display_upd_value("PxRcConfig[PDRC]", 1,
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original->PxRcConfig[PCH_PDRC],
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params->PxRcConfig[PCH_PDRC]);
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soc_display_upd_value("PxRcConfig[PERC]", 1,
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original->PxRcConfig[PCH_PERC],
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params->PxRcConfig[PCH_PERC]);
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soc_display_upd_value("PxRcConfig[PFRC]", 1,
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original->PxRcConfig[PCH_PFRC],
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params->PxRcConfig[PCH_PFRC]);
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soc_display_upd_value("PxRcConfig[PGRC]", 1,
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original->PxRcConfig[PCH_PGRC],
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params->PxRcConfig[PCH_PGRC]);
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soc_display_upd_value("PxRcConfig[PHRC]", 1,
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original->PxRcConfig[PCH_PHRC],
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params->PxRcConfig[PCH_PHRC]);
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soc_display_upd_value("GpioIrqRoute", 1,
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original->GpioIrqRoute,
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params->GpioIrqRoute);
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soc_display_upd_value("SciIrqSelect", 1,
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original->SciIrqSelect,
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params->SciIrqSelect);
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soc_display_upd_value("TcoIrqSelect", 1,
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original->TcoIrqSelect,
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params->TcoIrqSelect);
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soc_display_upd_value("TcoIrqEnable", 1,
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original->TcoIrqEnable,
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params->TcoIrqEnable);
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}
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static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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