From d125566582fd0902735bf963df777b1bc6faba1e Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Mon, 25 Oct 2021 20:48:56 -0600 Subject: [PATCH] mb/google/guybrush: Reconfigure GPIO_5 On Guybrush, pen is stuffed and GPIO_5 is used to enable Pen power. On Nipperkin board version 1, pen is not stuffed and instead the GPIO is used to control LCD Privacy settings. On upcoming Nipperkin board versions and other variants, GPIO_5 is not used. Configure GPIO_5 accordingly. BUG=b:202992077 TEST=Build and boot to OS in Guybrush. Ensure that the configuration is retained on existing boards. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I2aa2f16282b91f157701212ee27ddd2e89918767 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58597 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Rob Barnes --- .../google/guybrush/variants/baseboard/gpio.c | 4 ++-- .../google/guybrush/variants/guybrush/gpio.c | 11 ++++++++++- .../google/guybrush/variants/nipperkin/gpio.c | 2 ++ 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/guybrush/variants/baseboard/gpio.c b/src/mainboard/google/guybrush/variants/baseboard/gpio.c index 2fa525486e..376cf4ab0d 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/gpio.c +++ b/src/mainboard/google/guybrush/variants/baseboard/gpio.c @@ -21,8 +21,8 @@ static const struct soc_amd_gpio base_gpio_table[] = { PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), /* SOC_PEN_DETECT_ODL */ PAD_WAKE(GPIO_4, PULL_NONE, EDGE_HIGH, S0i3), - /* EN_PP5000_PEN */ - PAD_GPO(GPIO_5, HIGH), + /* Unused */ + PAD_NC(GPIO_5), /* EN_PP3300_WLAN */ PAD_GPO(GPIO_6, HIGH), /* EN_PP3300_TCHPAD */ diff --git a/src/mainboard/google/guybrush/variants/guybrush/gpio.c b/src/mainboard/google/guybrush/variants/guybrush/gpio.c index 08289c8bc9..fa3a8226f9 100644 --- a/src/mainboard/google/guybrush/variants/guybrush/gpio.c +++ b/src/mainboard/google/guybrush/variants/guybrush/gpio.c @@ -17,6 +17,14 @@ static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = { PAD_GPO(GPIO_70, HIGH), /* RAM_ID_CHAN_SEL */ PAD_GPI(GPIO_74, PULL_NONE), + /* EN_PP5000_PEN */ + PAD_GPO(GPIO_5, HIGH), +}; + +/* This table is used by guybrush variant with board version >= 2. */ +static const struct soc_amd_gpio bid2_ramstage_gpio_table[] = { + /* EN_PP5000_PEN */ + PAD_GPO(GPIO_5, HIGH), }; /* This table is used by guybrush variant with board version < 2. */ @@ -42,7 +50,8 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) return bid1_ramstage_gpio_table; } - return NULL; + *size = ARRAY_SIZE(bid2_ramstage_gpio_table); + return bid2_ramstage_gpio_table; } const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size) diff --git a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c index acdcc4f7f3..31fedad66a 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/gpio.c +++ b/src/mainboard/google/guybrush/variants/nipperkin/gpio.c @@ -12,6 +12,8 @@ static const struct soc_amd_gpio override_gpio_table[] = { /* Unused TP1063 */ PAD_NC(GPIO_17), PAD_NC(GPIO_18), + /* LCD_PRIVACY_PCH */ + PAD_GPO(GPIO_5, HIGH), }; static const struct soc_amd_gpio override_early_gpio_table[] = {