sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/system76/cannonlake/dt: Use comma separated list for arrays

Browse Source 
In order to improve the readability of the settings, use a comma
separated list to assign values to their indexes instead of repeating
the option name for each index.

Don't convert the settings for PCIe root ports as they should stay in
the device scope of them.

While on it, remove superfluous comments related to modified lines.

Change-Id: I92414efc9ddb849ceb8b9c4f0bc564bdbd92773b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78638
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer 2023-10-26 15:02:46 +02:00 committed by Felix Singer
parent 1fd4d76043
commit d163253ba0
9 changed files with 183 additions and 149 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
src/mainboard/system76/addw1/devicetree.cb
View File

@ -66,23 +66,25 @@ chip soc/intel/cannonlake
device pci 12.6 off end # GSPI #2 device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI device pci 14.0 on # USB xHCI
# USB2 register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort [0] = USB2_PORT_TYPE_C(OC_SKIP), /* USB 3.1 Gen 2 TYPE-C and DisplayPort */
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C [1] = USB2_PORT_TYPE_C(OC_SKIP), /* USB 3.1 Gen 2 TYPE-C */
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 2 [2] = USB2_PORT_MID(OC_SKIP), /* USB 3.1 Gen 2 */
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 audio [4] = USB2_PORT_MID(OC_SKIP), /* USB 3.1 Gen 1 audio */
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 Gen 1 back [5] = USB2_PORT_MID(OC_SKIP), /* USB 3.1 Gen 1 back */
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint [6] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Per-Key RGB keyboard [7] = USB2_PORT_MID(OC_SKIP), /* Per-Key RGB keyboard */
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Camera [8] = USB2_PORT_MID(OC_SKIP), /* Camera */
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
# USB3 }"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C and DisplayPort register "usb3_ports" = "{
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 right [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.1 Gen 2 TYPE-C and DisplayPort */
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT) [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.1 Gen 2 right */
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 2 TYPE-C (without TBT) [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.1 Gen 2 TYPE-C (without TBT) */
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 audio [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.1 Gen 2 TYPE-C (without TBT) */
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 Gen 1 back [4] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.1 Gen 1 audio */
[5] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3.1 Gen 1 back */
}"
end end
device pci 14.2 on end # Shared SRAM device pci 14.2 on end # Shared SRAM
device pci 14.3 on # CNVi wifi device pci 14.3 on # CNVi wifi
@ -103,8 +105,10 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3 device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4 device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA device pci 17.0 on # SATA
register "SataPortsEnable[0]" = "1" # HDD (SATA0B) register "SataPortsEnable" = "{
register "SataPortsEnable[1]" = "1" # SSD1 (SATA1A) [0] = 1, /* HDD (SATA0B) */
[1] = 1, /* SSD1 (SATA1A) */
}"
end end
device pci 19.2 off end # UART #2 device pci 19.2 off end # UART #2
device pci 1a.0 off end # eMMC device pci 1a.0 off end # eMMC

44
src/mainboard/system76/bonw14/devicetree.cb
View File

@ -73,23 +73,25 @@ chip soc/intel/cannonlake
device pci 12.6 off end # GSPI #2 device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI device pci 14.0 on # USB xHCI
# USB2 register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_2 [0] = USB2_PORT_MID(OC_SKIP), /* USB 3_2 */
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_1 [1] = USB2_PORT_MID(OC_SKIP), /* USB 3_1 */
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_4 [2] = USB2_PORT_MID(OC_SKIP), /* USB 3_4 */
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3_3 [3] = USB2_PORT_MID(OC_SKIP), /* USB 3_3 */
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB [4] = USB2_PORT_MID(OC_SKIP), /* Per-key RGB */
register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C [5] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C */
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # XFI [6] = USB2_PORT_MID(OC_SKIP), /* XFI */
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Light guide [8] = USB2_PORT_MID(OC_SKIP), /* Light guide */
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint [9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
# USB3 }"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_2 register "usb3_ports" = "{
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # ANX7440 [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3_2 */
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_4 [1] = USB3_PORT_DEFAULT(OC_SKIP), /* ANX7440 */
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3_3 [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3_4 */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3_3 */
}"
end end
device pci 14.2 on end # Shared SRAM device pci 14.2 on end # Shared SRAM
device pci 14.3 on # CNVi wifi device pci 14.3 on # CNVi wifi
@ -119,9 +121,11 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3 device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4 device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA device pci 17.0 on # SATA
register "SataPortsEnable[1]" = "1" # SATA1A (SSD) register "SataPortsEnable" = "{
register "SataPortsEnable[3]" = "1" # SATA3 (M.2_SATA3) [1] = 1, /* SATA1A (SSD) */
register "SataPortsEnable[4]" = "1" # SATA4 (SSD2) [3] = 1, /* SATA3 (M.2_SATA3) */
[4] = 1, /* SATA4 (SSD2) */
}"
end end
device pci 19.2 off end # UART #2 device pci 19.2 off end # UART #2
device pci 1a.0 off end # eMMC device pci 1a.0 off end # eMMC

36
src/mainboard/system76/cml-u/variants/darp6/overridetree.cb
View File

@ -3,20 +3,22 @@ chip soc/intel/cannonlake
subsystemid 0x1558 0x1404 inherit subsystemid 0x1558 0x1404 inherit
device pci 14.0 on # USB xHCI device pci 14.0 on # USB xHCI
# USB2 register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 [0] = USB2_PORT_MID(OC_SKIP), /* Type-A port 1 */
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE [1] = USB2_PORT_MID(OC_SKIP), /* 3G / LTE */
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 3 [2] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C port 3 */
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB Board port 4 [3] = USB2_PORT_MID(OC_SKIP), /* USB Board port 4 */
register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera [6] = USB2_PORT_MAX(OC_SKIP), /* Camera */
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
# USB3 }"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 register "usb3_ports" = "{
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A port 1 */
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 3 [1] = USB3_PORT_DEFAULT(OC_SKIP), /* 4G */
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Board port 4 [2] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C port 3 */
register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Board port 4 */
register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT [4] = USB3_PORT_EMPTY, /* Used by TBT */
[5] = USB3_PORT_EMPTY, /* Used by TBT */
}"
end end
device pci 15.0 on # I2C #0 device pci 15.0 on # I2C #0
chip drivers/i2c/hid chip drivers/i2c/hid
@ -29,8 +31,10 @@ chip soc/intel/cannonlake
end end
end end
device pci 17.0 on # SATA device pci 17.0 on # SATA
register "SataPortsEnable[0]" = "1" register "SataPortsEnable" = "{
register "SataPortsEnable[2]" = "1" [0] = 1,
[2] = 1,
}"
end end
device pci 1c.4 on # PCI Express Port 5 device pci 1c.4 on # PCI Express Port 5
# PCI Express Root port #5 x4, Clock 4 (TBT) # PCI Express Root port #5 x4, Clock 4 (TBT)

36
src/mainboard/system76/cml-u/variants/galp4/overridetree.cb
View File

@ -3,27 +3,31 @@ chip soc/intel/cannonlake
subsystemid 0x1558 0x1403 inherit subsystemid 0x1558 0x1403 inherit
device pci 14.0 on # USB xHCI device pci 14.0 on # USB xHCI
# USB2 register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 [0] = USB2_PORT_MID(OC_SKIP), /* Type-A port 1 */
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE [1] = USB2_PORT_MID(OC_SKIP), /* 3G / LTE */
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 3 [2] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C port 3 */
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB Board port 4 [3] = USB2_PORT_MID(OC_SKIP), /* USB Board port 4 */
register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera [6] = USB2_PORT_MAX(OC_SKIP), /* Camera */
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
# USB3 }"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 register "usb3_ports" = "{
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A port 1 */
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 3 [1] = USB3_PORT_DEFAULT(OC_SKIP), /* 4G */
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Board port 4 [2] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C port 3 */
register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Board port 4 */
register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT [4] = USB3_PORT_EMPTY, /* Used by TBT */
[5] = USB3_PORT_EMPTY, /* Used by TBT */
}"
end end
device pci 15.0 on # I2C #0 device pci 15.0 on # I2C #0
# I2C HID not supported on galp4 # I2C HID not supported on galp4
end end
device pci 17.0 on # SATA device pci 17.0 on # SATA
register "SataPortsEnable[0]" = "1" register "SataPortsEnable" = "{
register "SataPortsEnable[2]" = "1" [0] = 1,
[2] = 1,
}"
end end
device pci 1c.4 on # PCI Express Port 5 device pci 1c.4 on # PCI Express Port 5
# PCI Express Root port #5 x4, Clock 4 (TBT) # PCI Express Root port #5 x4, Clock 4 (TBT)

36
src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb
View File

@ -3,16 +3,18 @@ chip soc/intel/cannonlake
subsystemid 0x1558 0x1401 inherit subsystemid 0x1558 0x1401 inherit
device pci 14.0 on # USB xHCI device pci 14.0 on # USB xHCI
# USB2 register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 [0] = USB2_PORT_MID(OC_SKIP), /* Type-A port 1 */
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2 [1] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C port 2 */
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 3 [2] = USB2_PORT_MID(OC_SKIP), /* Type-A port 3 */
register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera [6] = USB2_PORT_MAX(OC_SKIP), /* Camera */
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
# USB3 }"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 register "usb3_ports" = "{
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2 [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A port 1 */
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C port 2 */
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A port 3 */
}"
end end
device pci 15.0 on # I2C #0 device pci 15.0 on # I2C #0
chip drivers/i2c/hid chip drivers/i2c/hid
@ -26,12 +28,14 @@ chip soc/intel/cannonlake
end end
device pci 17.0 on # SATA device pci 17.0 on # SATA
register "SataSalpSupport" = "1" register "SataSalpSupport" = "1"
# Port 2 (J_SSD2) register "SataPortsEnable" = "{
register "SataPortsEnable[1]" = "1" [1] = 1, /* Port 2 (J_SSD2) */
register "SataPortsDevSlp[1]" = "1" [2] = 1, /* Port 3 (J_SSD1) */
# Port 3 (J_SSD1) }"
register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp" = "{
register "SataPortsDevSlp[2]" = "1" [1] = 1, /* Port 2 (J_SSD2) */
[2] = 1, /* Port 3 (J_SSD1) */
}"
end end
device pci 1c.5 on # PCI Express Port 6 device pci 1c.5 on # PCI Express Port 6
device pci 00.0 on end # x1 Card reader device pci 00.0 on end # x1 Card reader

34
src/mainboard/system76/gaze15/devicetree.cb
View File

@ -67,19 +67,21 @@ chip soc/intel/cannonlake
device pci 12.6 off end # GSPI #2 device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI device pci 14.0 on # USB xHCI
# USB2 register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right [0] = USB2_PORT_MID(OC_SKIP), /* USB 3 Right */
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left [1] = USB2_PORT_MID(OC_SKIP), /* USB 3 Left */
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C [2] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C */
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB 2 Left [5] = USB2_PORT_MID(OC_SKIP), /* USB 2 Left */
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint [9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
# USB3 }"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right register "usb3_ports" = "{
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3 Right */
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3 Left */
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C [2] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C */
}"
end end
device pci 14.1 off end # USB xDCI (OTG) device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Shared SRAM device pci 14.2 on end # Shared SRAM
@ -100,8 +102,10 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3 device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4 device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA device pci 17.0 on # SATA
register "SataPortsEnable[1]" = "1" # SSD (SATA1A) register "SataPortsEnable" = "{
register "SataPortsEnable[4]" = "1" # HDD (SATA4) [1] = 1, /* SSD (SATA1A) */
[4] = 1, /* HDD (SATA4) */
}"
end end
device pci 19.0 off end # I2C #4 device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5 device pci 19.1 off end # I2C #5

40
src/mainboard/system76/oryp5/devicetree.cb
View File

@ -75,22 +75,24 @@ chip soc/intel/cannonlake
device pci 12.6 off end # GSPI #2 device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI device pci 14.0 on # USB xHCI
# USB2 register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C [0] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C */
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C/DP [1] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C/DP */
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right [2] = USB2_PORT_MID(OC_SKIP), /* USB 3 Right */
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left [3] = USB2_PORT_MID(OC_SKIP), /* USB 3 Left */
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB [4] = USB2_PORT_MID(OC_SKIP), /* Per-key RGB */
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE [6] = USB2_PORT_MID(OC_SKIP), /* 3G/LTE */
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint [9] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # WLAN/Bluetooth [13] = USB2_PORT_MID(OC_SKIP), /* WLAN/Bluetooth */
# USB3 }"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C register "usb3_ports" = "{
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C/DP [0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C */
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Right [1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C/DP */
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3 Right */
register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3 Left */
[6] = USB3_PORT_DEFAULT(OC_SKIP), /* 3G/LTE */
}"
end end
device pci 14.1 off end # USB xDCI (OTG) device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Shared SRAM device pci 14.2 on end # Shared SRAM
@ -113,8 +115,10 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3 device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4 device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA device pci 17.0 on # SATA
register "SataPortsEnable[1]" = "1" # SSD (SATA1A) register "SataPortsEnable" = "{
register "SataPortsEnable[4]" = "1" # HDD (SATA4) [1] = 1, /* SSD (SATA1A) */
[4] = 1, /* HDD (SATA4) */
}"
end end
device pci 19.0 off end # I2C #4 device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5 device pci 19.1 off end # I2C #5

28
src/mainboard/system76/oryp6/devicetree.cb
View File

@ -72,19 +72,21 @@ chip soc/intel/cannonlake
device pci 12.6 off end # GSPI #2 device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI device pci 14.0 on # USB xHCI
# USB2 register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Left [0] = USB2_PORT_MID(OC_SKIP), /* USB 3 Left */
register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C [1] = USB2_PORT_TYPE_C(OC_SKIP), /* Type-C */
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right 1 [2] = USB2_PORT_MID(OC_SKIP), /* USB 3 Right 1 */
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB 3 Right 2 [3] = USB2_PORT_MID(OC_SKIP), /* USB 3 Right 2 */
register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Per-key RGB [4] = USB2_PORT_MID(OC_SKIP), /* Per-key RGB */
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera [7] = USB2_PORT_MID(OC_SKIP), /* Camera */
register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint [10] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth [13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
# USB3 }"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 Left register "usb3_ports" = "{
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 right 1 [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3 Left */
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3 right 2 [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3 right 1 */
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3 right 2 */
}"
end end
device pci 14.1 off end # USB xDCI (OTG) device pci 14.1 off end # USB xDCI (OTG)
device pci 14.2 on end # Shared SRAM device pci 14.2 on end # Shared SRAM

36
src/mainboard/system76/whl-u/devicetree.cb
View File

@ -69,20 +69,22 @@ chip soc/intel/cannonlake
device pci 12.6 off end # GSPI #2 device pci 12.6 off end # GSPI #2
device pci 13.0 off end # Integrated Sensor Hub device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI device pci 14.0 on # USB xHCI
# USB2 register "usb2_ports" = "{
register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB-A [0] = USB2_PORT_MID(OC_SKIP), /* USB-A */
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE [1] = USB2_PORT_MID(OC_SKIP), /* 3G / LTE */
register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C [2] = USB2_PORT_TYPE_C(OC_SKIP), /* USB-C */
register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB-A [3] = USB2_PORT_MID(OC_SKIP), /* USB-A */
register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera [6] = USB2_PORT_MAX(OC_SKIP), /* Camera */
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
# USB3 }"
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A register "usb3_ports" = "{
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G on galp3-c, NC on darp5 [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-A */
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C [1] = USB3_PORT_DEFAULT(OC_SKIP), /* 4G on galp3-c, NC on darp5 */
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A [2] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-C */
register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT [3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB-A */
register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT [4] = USB3_PORT_EMPTY, /* Used by TBT */
[5] = USB3_PORT_EMPTY, /* Used by TBT */
}"
end end
device pci 14.1 off end # USB xDCI (OTG) device pci 14.1 off end # USB xDCI (OTG)
device pci 14.3 on # CNVi wifi device pci 14.3 on # CNVi wifi
@ -103,8 +105,10 @@ chip soc/intel/cannonlake
device pci 16.4 off end # Management Engine Interface 3 device pci 16.4 off end # Management Engine Interface 3
device pci 16.5 off end # Management Engine Interface 4 device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA device pci 17.0 on # SATA
register "SataPortsEnable[0]" = "1" register "SataPortsEnable" = "{
register "SataPortsEnable[2]" = "1" [0] = 1,
[2] = 1,
}"
end end
device pci 19.0 off end # I2C #4 device pci 19.0 off end # I2C #4
device pci 19.1 off end # I2C #5 device pci 19.1 off end # I2C #5