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soc/amd/stoneyridge/include/iomap: rename I2C[ABCD]_BASE_ADDRESS defines

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Picasso and Cezanne define and use APU_I2C[01234]_BASE for the base
addresses of the I2C controllers, so align Stoneyridge with this. The
ACPI device names aren't changed from I2C[ABCD] to I2C[0123] for now
since this might change behavior in the OS and would also change the
resulting binary of a timeless build.

TEST=Timeless build results in identical image for Google/Treeya.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9c400c073eba5c14bd35703b717f75df89a8719d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58370
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held
2021-10-15 16:29:22 +02:00
committed by Felix Held
parent 9c19bf090e
commit d1da9570da
5 changed files with 17 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/google/kahlee/variants/treeya/audio.c
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@@ -23,7 +23,7 @@ void variant_devtree_update(void)
printk(BIOS_INFO, "Checking audio codec\n"); printk(BIOS_INFO, "Checking audio codec\n");
return; return;
} }
} while (mmio_dev->path.mmio.addr != I2CA_BASE_ADDRESS); } while (mmio_dev->path.mmio.addr != APU_I2C0_BASE);
while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) { while ((child = dev_bus_each_child(mmio_dev->link_list, child)) != NULL) {
if (child->path.type != DEVICE_PATH_I2C) if (child->path.type != DEVICE_PATH_I2C)

8
src/soc/amd/stoneyridge/acpi/sb_fch.asl
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@@ -74,7 +74,7 @@ Device (I2CA) {
Name (_CRS, ResourceTemplate() Name (_CRS, ResourceTemplate()
{ {
IRQ (Edge, ActiveHigh, Exclusive) { 3 } IRQ (Edge, ActiveHigh, Exclusive) { 3 }
Memory32Fixed (ReadWrite, I2CA_BASE_ADDRESS, 0x1000) Memory32Fixed (ReadWrite, APU_I2C0_BASE, 0x1000)
}) })
Method (_STA, 0x0, NotSerialized) Method (_STA, 0x0, NotSerialized)
@@ -90,7 +90,7 @@ Device (I2CB)
Name (_CRS, ResourceTemplate() Name (_CRS, ResourceTemplate()
{ {
IRQ (Edge, ActiveHigh, Exclusive) { 15 } IRQ (Edge, ActiveHigh, Exclusive) { 15 }
Memory32Fixed (ReadWrite, I2CB_BASE_ADDRESS, 0x1000) Memory32Fixed (ReadWrite, APU_I2C1_BASE, 0x1000)
}) })
Method (_STA, 0x0, NotSerialized) Method (_STA, 0x0, NotSerialized)
{ {
@@ -104,7 +104,7 @@ Device (I2CC) {
Name (_CRS, ResourceTemplate() Name (_CRS, ResourceTemplate()
{ {
IRQ (Edge, ActiveHigh, Exclusive) { 6 } IRQ (Edge, ActiveHigh, Exclusive) { 6 }
Memory32Fixed (ReadWrite, I2CC_BASE_ADDRESS, 0x1000) Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000)
}) })
Method (_STA, 0x0, NotSerialized) Method (_STA, 0x0, NotSerialized)
@@ -119,7 +119,7 @@ Device (I2CD)
Name (_UID, 0x3) Name (_UID, 0x3)
Name (_CRS, ResourceTemplate() { Name (_CRS, ResourceTemplate() {
IRQ (Edge, ActiveHigh, Exclusive) { 14 } IRQ (Edge, ActiveHigh, Exclusive) { 14 }
Memory32Fixed(ReadWrite, I2CD_BASE_ADDRESS, 0x1000) Memory32Fixed(ReadWrite, APU_I2C3_BASE, 0x1000)
}) })
Method (_STA, 0x0, NotSerialized) Method (_STA, 0x0, NotSerialized)
{ {

8
src/soc/amd/stoneyridge/chip.c
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@@ -101,10 +101,10 @@ static struct device_operations pci_domain_ops = {
static void set_mmio_dev_ops(struct device *dev) static void set_mmio_dev_ops(struct device *dev)
{ {
switch (dev->path.mmio.addr) { switch (dev->path.mmio.addr) {
case I2CA_BASE_ADDRESS: case APU_I2C0_BASE:
case I2CB_BASE_ADDRESS: case APU_I2C1_BASE:
case I2CC_BASE_ADDRESS: case APU_I2C2_BASE:
case I2CD_BASE_ADDRESS: case APU_I2C3_BASE:
dev->ops = &soc_amd_i2c_mmio_ops; dev->ops = &soc_amd_i2c_mmio_ops;
break; break;
} }

8
src/soc/amd/stoneyridge/i2c.c
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@@ -7,10 +7,10 @@
#include "chip.h" #include "chip.h"
static const struct soc_i2c_ctrlr_info i2c_ctrlr[] = { static const struct soc_i2c_ctrlr_info i2c_ctrlr[] = {
{ I2C_MASTER_MODE, I2CA_BASE_ADDRESS, "I2CA" }, { I2C_MASTER_MODE, APU_I2C0_BASE, "I2CA" },
{ I2C_MASTER_MODE, I2CB_BASE_ADDRESS, "I2CB" }, { I2C_MASTER_MODE, APU_I2C1_BASE, "I2CB" },
{ I2C_MASTER_MODE, I2CC_BASE_ADDRESS, "I2CC" }, { I2C_MASTER_MODE, APU_I2C2_BASE, "I2CC" },
{ I2C_MASTER_MODE, I2CD_BASE_ADDRESS, "I2CD" }, { I2C_MASTER_MODE, APU_I2C3_BASE, "I2CD" },
}; };
const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs) const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)

8
src/soc/amd/stoneyridge/include/soc/iomap.h
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@@ -11,10 +11,10 @@
#define ALINK_AHB_ADDRESS 0xfedc0000 #define ALINK_AHB_ADDRESS 0xfedc0000
/* I2C fixed address */ /* I2C fixed address */
#define I2CA_BASE_ADDRESS 0xfedc2000 #define APU_I2C0_BASE 0xfedc2000
#define I2CB_BASE_ADDRESS 0xfedc3000 #define APU_I2C1_BASE 0xfedc3000
#define I2CC_BASE_ADDRESS 0xfedc4000 #define APU_I2C2_BASE 0xfedc4000
#define I2CD_BASE_ADDRESS 0xfedc5000 #define APU_I2C3_BASE 0xfedc5000
#if CONFIG(HPET_ADDRESS_OVERRIDE) #if CONFIG(HPET_ADDRESS_OVERRIDE)
#error HPET address override is not allowed and must be fixed at 0xfed00000 #error HPET address override is not allowed and must be fixed at 0xfed00000