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mb/goog/brya: unlock gpio wake sources

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The power off code in depthcharge disables all GPEs prior to power off.
The problem is that for gpio wake sources that are locked, this power
off code cannot successfully clear any pending interrupt from that
source.  This can result in the device incorrectly waking back up after
it's been powered off from the firmware dev screen.

BUG=b:360380950, b:359692570
BRANCH=firmware-brya-14505.B
TEST=verify brask, nissa, or brya DUT is able to power down and stay
powered down when selecting the "Power off" button in the firmware dev
screen.

Change-Id: Ic0ac73f8f29761f072d42f35e97198b56d32a9bc
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Nick Vaccaro 2024-08-16 18:05:07 -07:00 committed by Felix Held
parent 97df9ef25f
commit d1ed56e81a
4 changed files with 7 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/brya/variants/baseboard/brask/gpio.c
View File

@ -239,11 +239,11 @@ static const struct pad_config gpio_table[] = {
/* F14 : GSXDIN ==> EN_PP3300_SSD */ /* F14 : GSXDIN ==> EN_PP3300_SSD */
PAD_CFG_GPO_LOCK(GPP_F14, 1, LOCK_CONFIG), PAD_CFG_GPO_LOCK(GPP_F14, 1, LOCK_CONFIG),
/* F15 : GSXSRESET# ==> FPMCU_INT_L */ /* F15 : GSXSRESET# ==> FPMCU_INT_L */
PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG), PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, PWROK, LEVEL, INVERT),
/* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */
PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG),
/* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */
PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG), PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, PWROK, LEVEL, INVERT),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
/* F19 : SRCCLKREQ6# ==> LAN_CLKREQ_ODL */ /* F19 : SRCCLKREQ6# ==> LAN_CLKREQ_ODL */

2
src/mainboard/google/brya/variants/baseboard/nissa/gpio.c
View File

@ -242,7 +242,7 @@ static const struct pad_config gpio_table[] = {
/* F16 : NC */ /* F16 : NC */
PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
/* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */ /* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG), PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, PWROK, EDGE_SINGLE, INVERT),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
/* F19 : Not available */ /* F19 : Not available */

4
src/mainboard/google/brya/variants/orisa/gpio.c
View File

@ -58,7 +58,7 @@ static const struct pad_config gpio_table[] = {
/* B2 : NC */ /* B2 : NC */
PAD_NC(GPP_B2, NONE), PAD_NC(GPP_B2, NONE),
/* B3 : CPU_GP2 ==> EC_TP_INT */ /* B3 : CPU_GP2 ==> EC_TP_INT */
PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_B3, NONE, LEVEL, INVERT, LOCK_CONFIG), PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PWROK, LEVEL, INVERT),
/* B4 : PROC_GP3 ==> EN_PP3300_UCAM_X */ /* B4 : PROC_GP3 ==> EN_PP3300_UCAM_X */
PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
/* B5 : GPP_B5 ==> ISH_I2C0_SCL */ /* B5 : GPP_B5 ==> ISH_I2C0_SCL */
@ -242,7 +242,7 @@ static const struct pad_config gpio_table[] = {
/* F16 : NC */ /* F16 : NC */
PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
/* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */ /* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG), PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, PWROK, EDGE_SINGLE, INVERT),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
/* F19 : Not available */ /* F19 : Not available */

4
src/mainboard/google/brya/variants/trulo/gpio.c
View File

@ -58,7 +58,7 @@ static const struct pad_config gpio_table[] = {
/* B2 : NC */ /* B2 : NC */
PAD_NC(GPP_B2, NONE), PAD_NC(GPP_B2, NONE),
/* B3 : CPU_GP2 ==> EC_TP_INT */ /* B3 : CPU_GP2 ==> EC_TP_INT */
PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_B3, NONE, LEVEL, INVERT, LOCK_CONFIG), PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PWROK, LEVEL, INVERT),
/* B4 : PROC_GP3 ==> EN_PP3300_UCAM_X */ /* B4 : PROC_GP3 ==> EN_PP3300_UCAM_X */
PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
/* B5 : GPP_B5 ==> ISH_I2C0_SCL */ /* B5 : GPP_B5 ==> ISH_I2C0_SCL */
@ -242,7 +242,7 @@ static const struct pad_config gpio_table[] = {
/* F16 : NC */ /* F16 : NC */
PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
/* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */ /* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */
PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, EDGE_SINGLE, INVERT, LOCK_CONFIG), PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, PWROK, EDGE_SINGLE, INVERT),
/* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG),
/* F19 : Not available */ /* F19 : Not available */