arm(64): Replace write32() and friends with writel()
This patch is a raw application of the following spatch to the
directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>,
src/soc/<arm(64)-soc> and src/drivers/gic:
@@
expression A, V;
@@
- write32(V, A)
+ writel(V, A)
@@
expression A, V;
@@
- write16(V, A)
+ writew(V, A)
@@
expression A, V;
@@
- write8(V, A)
+ writeb(V, A)
This replaces all uses of write{32,16,8}() with write{l,w,b}()
which is currently equivalent and much more common. This is a
preparatory step that will allow us to easier flip them all at once to
the new write32(a,v) model.
BRANCH=none
BUG=chromium:451388
TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky.
Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24
Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254862
Reviewed-on: http://review.coreboot.org/9834
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Julius Werner
committed by
Patrick Georgi
Patrick Georgi
parent
24f9476531
commit
d21a329866
@@ -28,7 +28,7 @@ void a1x_periph_clock_enable(enum a1x_clken periph)
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addr = (void *)A1X_CCM_BASE + (periph >> 5);
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reg32 = read32(addr);
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reg32 |= 1 << (periph & 0x1f);
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write32(reg32, addr);
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writel(reg32, addr);
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}
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/**
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@@ -44,7 +44,7 @@ void a1x_periph_clock_disable(enum a1x_clken periph)
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addr = (void *)A1X_CCM_BASE + (periph >> 5);
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reg32 = read32(addr);
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reg32 &= ~(1 << (periph & 0x1f));
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write32(reg32, addr);
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writel(reg32, addr);
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}
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/**
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@@ -88,7 +88,7 @@ void a1x_pll5_configure(u8 mul_n, u8 mul_k, u8 div_m, u8 exp_div_p)
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reg32 |= (PLL5_FACTOR_M(div_m) | PLL5_FACTOR_N(mul_n) |
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PLL5_FACTOR_K(mul_k) | PLL5_DIV_EXP_P(exp_div_p));
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reg32 |= PLL5_PLL_ENABLE;
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write32(reg32, &ccm->pll5_cfg);
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writel(reg32, &ccm->pll5_cfg);
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}
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/**
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@@ -166,7 +166,7 @@ static void cpu_clk_src_switch(u32 clksel_bits)
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reg32 = read32(&ccm->cpu_ahb_apb0_cfg);
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reg32 &= ~CPU_CLK_SRC_MASK;
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reg32 |= clksel_bits & CPU_CLK_SRC_MASK;
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write32(reg32, &ccm->cpu_ahb_apb0_cfg);
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writel(reg32, &ccm->cpu_ahb_apb0_cfg);
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}
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static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp)
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@@ -179,7 +179,7 @@ static void change_sys_divisors(u8 axi, u8 ahb_exp, u8 apb0_exp)
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reg32 |= ((axi - 1) << 0) & AXI_DIV_MASK;
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reg32 |= (ahb_exp << 4) & AHB_DIV_MASK;
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reg32 |= (apb0_exp << 8) & APB0_DIV_MASK;
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write32(reg32, &ccm->cpu_ahb_apb0_cfg);
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writel(reg32, &ccm->cpu_ahb_apb0_cfg);
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}
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static void spin_delay(u32 loops)
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@@ -262,7 +262,7 @@ void a1x_set_cpu_clock(u16 cpu_clk_mhz)
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change_sys_divisors(axi, ahb_exp, apb0_exp);
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/* Configure PLL1 at the desired frequency */
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write32(pll1_table[i].pll1_cfg, &ccm->pll1_cfg);
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writel(pll1_table[i].pll1_cfg, &ccm->pll1_cfg);
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spin_delay(8);
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cpu_clk_src_switch(CPU_CLK_SRC_PLL1);
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@@ -76,7 +76,7 @@ void gpio_write(u8 port, u32 val)
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if ((port > GPS))
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return;
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write32(val, &gpio->port[port].dat);
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writel(val, &gpio->port[port].dat);
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}
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/**
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@@ -33,7 +33,7 @@ void gpio_set_pin_func(u8 port, u8 pin, u8 pad_func)
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reg32 = read32(&gpio->port[port].cfg[reg]);
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reg32 &= ~(0xf << bit);
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reg32 |= (pad_func & 0xf) << bit;
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write32(reg32, &gpio->port[port].cfg[reg]);
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writel(reg32, &gpio->port[port].cfg[reg]);
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}
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/**
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@@ -74,6 +74,6 @@ void gpio_set_multipin_func(u8 port, u32 pin_mask, u8 pad_func)
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reg32 &= ~(0xf << bit);
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reg32 |= (pad_func & 0xf) << bit;
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}
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write32(reg32, &gpio->port[port].cfg[reg]);
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writel(reg32, &gpio->port[port].cfg[reg]);
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}
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}
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@@ -118,7 +118,7 @@ static void mctl_configure_hostport(void)
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u32 i;
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for (i = 0; i < 32; i++)
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write32(hpcr_value[i], &dram->hpcr[i]);
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writel(hpcr_value[i], &dram->hpcr[i]);
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}
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static void mctl_setup_dram_clock(u32 clk)
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@@ -333,9 +333,9 @@ static void dramc_set_autorefresh_cycle(u32 clk)
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tmp_val = tmp_val * 9 - 200;
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reg32 |= tmp_val << 8;
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reg32 |= 0x8 << 24;
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write32(reg32, &dram->drr);
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writel(reg32, &dram->drr);
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} else {
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write32(0x0, &dram->drr);
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writel(0x0, &dram->drr);
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}
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}
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@@ -360,7 +360,7 @@ unsigned long dramc_init(struct dram_para *para)
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a1x_gate_dram_clock_output();
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/* select dram controller 1 */
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write32(DRAM_CSEL_MAGIC, &dram->csel);
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writel(DRAM_CSEL_MAGIC, &dram->csel);
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mctl_itm_disable();
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mctl_enable_dll0(para->tpr3);
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@@ -390,7 +390,7 @@ unsigned long dramc_init(struct dram_para *para)
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reg32 |= DRAM_DCR_RANK_SEL(para->rank_num - 1);
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reg32 |= DRAM_DCR_CMD_RANK_ALL;
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reg32 |= DRAM_DCR_MODE(DRAM_DCR_MODE_INTERLEAVE);
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write32(reg32, &dram->dcr);
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writel(reg32, &dram->dcr);
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/* dram clock on */
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a1x_ungate_dram_clock_output();
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@@ -405,21 +405,21 @@ unsigned long dramc_init(struct dram_para *para)
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reg32 = ((para->zq) >> 8) & 0xfffff;
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reg32 |= ((para->zq) & 0xff) << 20;
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reg32 |= (para->zq) & 0xf0000000;
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write32(reg32, &dram->zqcr0);
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writel(reg32, &dram->zqcr0);
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/* set I/O configure register */
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reg32 = 0x00cc0000;
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reg32 |= (para->odt_en) & 0x3;
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reg32 |= ((para->odt_en) & 0x3) << 30;
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write32(reg32, &dram->iocr);
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writel(reg32, &dram->iocr);
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/* set refresh period */
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dramc_set_autorefresh_cycle(para->clock);
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/* set timing parameters */
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write32(para->tpr0, &dram->tpr0);
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write32(para->tpr1, &dram->tpr1);
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write32(para->tpr2, &dram->tpr2);
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writel(para->tpr0, &dram->tpr0);
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writel(para->tpr1, &dram->tpr1);
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writel(para->tpr2, &dram->tpr2);
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if (para->type == DRAM_MEMORY_TYPE_DDR3) {
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reg32 = DRAM_MR_BURST_LENGTH(0x0);
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@@ -430,11 +430,11 @@ unsigned long dramc_init(struct dram_para *para)
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reg32 |= DRAM_MR_CAS_LAT(para->cas);
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reg32 |= DRAM_MR_WRITE_RECOVERY(0x5);
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}
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write32(reg32, &dram->mr);
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writel(reg32, &dram->mr);
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write32(para->emr1, &dram->emr);
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write32(para->emr2, &dram->emr2);
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write32(para->emr3, &dram->emr3);
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writel(para->emr1, &dram->emr);
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writel(para->emr2, &dram->emr2);
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writel(para->emr3, &dram->emr3);
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/* set DQS window mode */
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clrsetbits_le32(&dram->ccr, DRAM_CCR_DQS_DRIFT_COMP, DRAM_CCR_DQS_GATE);
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@@ -24,13 +24,13 @@ void init_timer(void)
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{
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u32 reg32;
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/* Load the timer rollover value */
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write32(0xffffffff, &tmr0->interval);
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writel(0xffffffff, &tmr0->interval);
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/* Configure the timer to run from 24MHz oscillator, no prescaler */
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reg32 = TIMER_CTRL_PRESC_DIV_EXP(0);
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reg32 |= TIMER_CTRL_CLK_SRC_OSC24M;
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reg32 |= TIMER_CTRL_RELOAD;
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reg32 |= TIMER_CTRL_TMR_EN;
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write32(reg32, &tmr0->ctrl);
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writel(reg32, &tmr0->ctrl);
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}
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void udelay(unsigned usec)
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@@ -61,6 +61,6 @@ void udelay(unsigned usec)
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*/
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u8 a1x_get_cpu_chip_revision(void)
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{
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write32(0, &timer_module->cpu_cfg);
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writel(0, &timer_module->cpu_cfg);
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return (read32(&timer_module->cpu_cfg) >> 6) & 0x3;
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}
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@@ -42,7 +42,7 @@ static void configure_clock(struct a1x_twi *twi, u32 speed_hz)
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/* Pre-divide the clock by 8 */
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n = 3;
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m = (apb_clk >> n) / speed_hz;
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write32(TWI_CLK_M(m) | TWI_CLK_N(n), &twi->clk);
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writel(TWI_CLK_M(m) | TWI_CLK_N(n), &twi->clk);
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}
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void a1x_twi_init(u8 bus, u32 speed_hz)
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@@ -53,9 +53,9 @@ void a1x_twi_init(u8 bus, u32 speed_hz)
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configure_clock(twi, speed_hz);
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/* Enable the I²C bus */
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write32(TWI_CTL_BUS_EN, &twi->ctl);
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writel(TWI_CTL_BUS_EN, &twi->ctl);
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/* Issue soft reset */
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write32(1, &twi->reset);
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writel(1, &twi->reset);
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while (i-- && read32(&twi->reset))
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udelay(1);
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@@ -63,12 +63,12 @@ void a1x_twi_init(u8 bus, u32 speed_hz)
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static void clear_interrupt_flag(struct a1x_twi *twi)
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{
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write32(read32(&twi->ctl) & ~TWI_CTL_INT_FLAG, &twi->ctl);
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writel(read32(&twi->ctl) & ~TWI_CTL_INT_FLAG, &twi->ctl);
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}
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static void i2c_send_data(struct a1x_twi *twi, u8 data)
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{
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write32(data, &twi->data);
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writel(data, &twi->data);
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clear_interrupt_flag(twi);
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}
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@@ -90,7 +90,7 @@ static void i2c_send_start(struct a1x_twi *twi)
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reg32 = read32(&twi->ctl);
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reg32 &= ~TWI_CTL_INT_FLAG;
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reg32 |= TWI_CTL_M_START;
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write32(reg32, &twi->ctl);
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writel(reg32, &twi->ctl);
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/* M_START is automatically cleared after condition is transmitted */
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i = TWI_TIMEOUT;
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@@ -106,7 +106,7 @@ static void i2c_send_stop(struct a1x_twi *twi)
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reg32 = read32(&twi->ctl);
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reg32 &= ~TWI_CTL_INT_FLAG;
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reg32 |= TWI_CTL_M_STOP;
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write32(reg32, &twi->ctl);
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writel(reg32, &twi->ctl);
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}
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static int i2c_read(struct a1x_twi *twi, uint8_t chip,
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@@ -22,10 +22,10 @@ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bit
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div = (u16) uart_baudrate_divisor(baud_rate,
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uart_platform_refclk(), 16);
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/* Enable access to Divisor Latch register */
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write32(UART8250_LCR_DLAB, &uart->lcr);
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writel(UART8250_LCR_DLAB, &uart->lcr);
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/* Set baudrate */
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write32((div >> 8) & 0xff, &uart->dlh);
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write32(div & 0xff, &uart->dll);
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writel((div >> 8) & 0xff, &uart->dlh);
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writel(div & 0xff, &uart->dll);
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/* Set line control */
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reg32 = (data_bits - 5) & UART8250_LCR_WLS_MSK;
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switch (parity) {
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@@ -40,12 +40,12 @@ static void a10_uart_configure(struct a10_uart *uart, u32 baud_rate, u8 data_bit
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default:
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break;
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}
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write32(reg32, &uart->lcr);
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writel(reg32, &uart->lcr);
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}
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static void a10_uart_enable_fifos(struct a10_uart *uart)
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{
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write32(UART8250_FCR_FIFO_EN, &uart->fcr);
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writel(UART8250_FCR_FIFO_EN, &uart->fcr);
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}
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static int tx_fifo_full(struct a10_uart *uart)
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@@ -83,7 +83,7 @@ static void a10_uart_tx_blocking(struct a10_uart *uart, u8 data)
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{
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while (tx_fifo_full(uart)) ;
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return write32(data, &uart->thr);
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return writel(data, &uart->thr);
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}
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@@ -42,88 +42,88 @@ static void am335x_uart_init(struct am335x_uart *uart, uint16_t div)
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uint16_t lcr_orig, efr_orig, mcr_orig;
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/* reset the UART */
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write16(uart->sysc | SYSC_SOFTRESET, &uart->sysc);
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writew(uart->sysc | SYSC_SOFTRESET, &uart->sysc);
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while (!(read16(&uart->syss) & SYSS_RESETDONE))
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;
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/* 1. switch to register config mode B */
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lcr_orig = read16(&uart->lcr);
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write16(0xbf, &uart->lcr);
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writew(0xbf, &uart->lcr);
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/*
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* 2. Set EFR ENHANCED_EN bit. To access this bit, registers must
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* be in TCR_TLR submode, meaning EFR[4] = 1 and MCR[6] = 1.
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*/
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efr_orig = read16(&uart->efr);
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write16(efr_orig | EFR_ENHANCED_EN, &uart->efr);
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writew(efr_orig | EFR_ENHANCED_EN, &uart->efr);
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/* 3. Switch to register config mode A */
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write16(0x80, &uart->lcr);
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writew(0x80, &uart->lcr);
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/* 4. Enable register submode TCR_TLR to access the UARTi.UART_TLR */
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mcr_orig = read16(&uart->mcr);
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write16(mcr_orig | MCR_TCR_TLR, &uart->mcr);
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writew(mcr_orig | MCR_TCR_TLR, &uart->mcr);
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/* 5. Enable the FIFO. For now we'll ignore FIFO triggers and DMA */
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write16(FCR_FIFO_EN, &uart->fcr);
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writew(FCR_FIFO_EN, &uart->fcr);
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/* 6. Switch to configuration mode B */
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write16(0xbf, &uart->lcr);
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writew(0xbf, &uart->lcr);
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/* Skip steps 7 and 8 (setting up FIFO triggers for DMA) */
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/* 9. Restore original EFR value */
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write16(efr_orig, &uart->efr);
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writew(efr_orig, &uart->efr);
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/* 10. Switch to config mode A */
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write16(0x80, &uart->lcr);
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writew(0x80, &uart->lcr);
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/* 11. Restore original MCR value */
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write16(mcr_orig, &uart->mcr);
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writew(mcr_orig, &uart->mcr);
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/* 12. Restore original LCR value */
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write16(lcr_orig, &uart->lcr);
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writew(lcr_orig, &uart->lcr);
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/* Protocol, baud rate and interrupt settings */
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/* 1. Disable UART access to DLL and DLH registers */
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write16(read16(&uart->mdr1) | 0x7, &uart->mdr1);
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writew(read16(&uart->mdr1) | 0x7, &uart->mdr1);
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/* 2. Switch to config mode B */
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write16(0xbf, &uart->lcr);
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writew(0xbf, &uart->lcr);
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/* 3. Enable access to IER[7:4] */
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write16(efr_orig | EFR_ENHANCED_EN, &uart->efr);
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writew(efr_orig | EFR_ENHANCED_EN, &uart->efr);
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/* 4. Switch to operational mode */
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write16(0x0, &uart->lcr);
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writew(0x0, &uart->lcr);
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/* 5. Clear IER */
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write16(0x0, &uart->ier);
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writew(0x0, &uart->ier);
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/* 6. Switch to config mode B */
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write16(0xbf, &uart->lcr);
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writew(0xbf, &uart->lcr);
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/* 7. Set dll and dlh to the desired values (table 19-25) */
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write16((div >> 8), &uart->dlh);
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write16((div & 0xff), &uart->dll);
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writew((div >> 8), &uart->dlh);
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writew((div & 0xff), &uart->dll);
|
||||
|
||||
/* 8. Switch to operational mode to access ier */
|
||||
write16(0x0, &uart->lcr);
|
||||
writew(0x0, &uart->lcr);
|
||||
|
||||
/* 9. Clear ier to disable all interrupts */
|
||||
write16(0x0, &uart->ier);
|
||||
writew(0x0, &uart->ier);
|
||||
|
||||
/* 10. Switch to config mode B */
|
||||
write16(0xbf, &uart->lcr);
|
||||
writew(0xbf, &uart->lcr);
|
||||
|
||||
/* 11. Restore efr */
|
||||
write16(efr_orig, &uart->efr);
|
||||
writew(efr_orig, &uart->efr);
|
||||
|
||||
/* 12. Set protocol formatting 8n1 (8 bit data, no parity, 1 stop bit) */
|
||||
write16(0x3, &uart->lcr);
|
||||
writew(0x3, &uart->lcr);
|
||||
|
||||
/* 13. Load the new UART mode */
|
||||
write16(0x0, &uart->mdr1);
|
||||
writew(0x0, &uart->mdr1);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -145,7 +145,7 @@ static void am335x_uart_tx_byte(struct am335x_uart *uart, unsigned char data)
|
||||
{
|
||||
while (!(read16(&uart->lsr) & LSR_TXFIFOE));
|
||||
|
||||
return write8(data, &uart->thr);
|
||||
return writeb(data, &uart->thr);
|
||||
}
|
||||
|
||||
unsigned int uart_platform_refclk(void)
|
||||
|
||||
Reference in New Issue
Block a user