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Remove drivers/pci/onboard. The only purpose was for option ROMs, which are

Browse Source 
now handled more generically using CBFS.

Simplify the option ROM code in device/pci_rom.c, since there are only two ways
to get a ROM address now (CBFS and the device) and add an exception for qemu.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
2009-11-06 23:42:26 +00:00
parent 547d48ab01
commit d27c08c289
107 changed files with 170 additions and 722 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
src/devices/pci_device.c
View File

@@ -285,11 +285,6 @@ static void pci_get_rom_resource(struct device *dev, unsigned long index)
unsigned long value; unsigned long value;
resource_t moving; resource_t moving;
if ((dev->on_mainboard) && (dev->rom_address == 0)) {
/* Skip it if rom_address is not set in the MB Config.lb. */
return;
}
/* Initialize the resources to nothing. */ /* Initialize the resources to nothing. */
resource = new_resource(dev, index); resource = new_resource(dev, index);
@@ -326,18 +321,6 @@ static void pci_get_rom_resource(struct device *dev, unsigned long index)
} }
resource->flags = 0; resource->flags = 0;
} }
/* For on board device with embedded ROM image, the ROM image is at
* fixed address specified in the Config.lb, the dev->rom_address is
* inited by driver_pci_onboard_ops::enable_dev() */
if ((dev->on_mainboard) && (dev->rom_address != 0)) {
resource->base = dev->rom_address;
/* The resource allocator needs the size to be non-zero. */
resource->size = 0x100;
resource->flags |= IORESOURCE_MEM | IORESOURCE_READONLY |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
compact_resources(dev); compact_resources(dev);
} }

55
src/devices/pci_rom.c
View File

@@ -31,42 +31,37 @@
struct rom_header * pci_rom_probe(struct device *dev) struct rom_header * pci_rom_probe(struct device *dev)
{ {
unsigned long rom_address = 0;
struct rom_header *rom_header; struct rom_header *rom_header;
struct pci_data *rom_data; struct pci_data *rom_data;
void *v; /* If it's in FLASH, then don't check device for ROM. */
/* if it's in FLASH, then it's as if dev->on_mainboard was true */ rom_header = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
v = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
printk_debug("In cbfs, rom address for %s = %p\n",
dev_path(dev), v);
if (v) {
dev->rom_address = (u32)v;
dev->on_mainboard = 1;
}
if (dev->on_mainboard) { if (rom_header) {
// in case some device PCI_ROM_ADDRESS can not be set or readonly printk_debug("In cbfs, rom address for %s = %p\n",
rom_address = dev->rom_address; dev_path(dev), rom_header);
printk_debug("On mainboard, rom address for %s = %lx\n",
dev_path(dev), rom_address);
} else { } else {
unsigned long rom_address;
rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS); rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS);
if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
#if CONFIG_BOARD_EMULATION_QEMU_X86
rom_address = 0xc0000;
#else
return NULL;
#endif
} else {
/* enable expansion ROM address decoding */
pci_write_config32(dev, PCI_ROM_ADDRESS,
rom_address|PCI_ROM_ADDRESS_ENABLE);
}
printk_debug("On card, rom address for %s = %lx\n", printk_debug("On card, rom address for %s = %lx\n",
dev_path(dev), rom_address); dev_path(dev), rom_address);
rom_header = (struct rom_header *)rom_address;
} }
if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
return NULL;
}
if(!dev->on_mainboard) {
/* enable expansion ROM address decoding */
pci_write_config32(dev, PCI_ROM_ADDRESS,
rom_address|PCI_ROM_ADDRESS_ENABLE);
}
rom_header = (struct rom_header *)rom_address;
printk_spew("PCI Expansion ROM, signature 0x%04x, INIT size 0x%04x, data ptr 0x%04x\n", printk_spew("PCI Expansion ROM, signature 0x%04x, INIT size 0x%04x, data ptr 0x%04x\n",
le32_to_cpu(rom_header->signature), le32_to_cpu(rom_header->signature),
rom_header->size * 512, le32_to_cpu(rom_header->data)); rom_header->size * 512, le32_to_cpu(rom_header->data));
@@ -76,11 +71,12 @@ struct rom_header * pci_rom_probe(struct device *dev)
return NULL; return NULL;
} }
rom_data = (struct pci_data *) ((void *)rom_header + le32_to_cpu(rom_header->data)); rom_data = (((void *)rom_header) + le32_to_cpu(rom_header->data));
printk_spew("PCI ROM Image, Vendor %04x, Device %04x,\n", printk_spew("PCI ROM Image, Vendor %04x, Device %04x,\n",
rom_data->vendor, rom_data->device); rom_data->vendor, rom_data->device);
if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) { if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) {
printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x\n", printk_err("ID mismatch: Vendor ID %04x, Device ID %04x\n",
rom_data->vendor, rom_data->device); rom_data->vendor, rom_data->device);
return NULL; return NULL;
} }
@@ -90,7 +86,8 @@ struct rom_header * pci_rom_probe(struct device *dev)
rom_data->type); rom_data->type);
if (dev->class != ((rom_data->class_hi << 8) | rom_data->class_lo)) { if (dev->class != ((rom_data->class_hi << 8) | rom_data->class_lo)) {
printk_debug("Class Code mismatch ROM %08x, dev %08x\n", printk_debug("Class Code mismatch ROM %08x, dev %08x\n",
(rom_data->class_hi << 8) | rom_data->class_lo, dev->class); (rom_data->class_hi << 8) | rom_data->class_lo,
dev->class);
//return NULL; //return NULL;
} }

1
src/drivers/Makefile.inc
View File

@@ -1,3 +1,2 @@
subdirs-y += pci
subdirs-y += generic/debug subdirs-y += generic/debug
subdirs-y += ati/ragexl subdirs-y += ati/ragexl

1
src/drivers/pci/Makefile.inc
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@@ -1 +0,0 @@
subdirs-y += onboard

4
src/drivers/pci/onboard/Config.lb
View File

@@ -1,4 +0,0 @@
config chip.h
object onboard.o

1
src/drivers/pci/onboard/Makefile.inc
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@@ -1 +0,0 @@
obj-y += onboard.o

11
src/drivers/pci/onboard/chip.h
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@@ -1,11 +0,0 @@
#ifndef PCI_ONBOARD_H
#define PCI_ONBOARD_H
struct drivers_pci_onboard_config
{
unsigned long rom_address;
};
struct chip_operations;
extern struct chip_operations drivers_pci_onboard_ops;
#endif

78
src/drivers/pci/onboard/onboard.c
View File

@@ -1,78 +0,0 @@
/*
* Copyright 2004 Tyan Computer
* by yhlu@tyan.com
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "chip.h"
/*
* How to use the onboard device driver for option rom execution:
*
* 1. You need to add the driver to your mainboard Config.lb:
*
* chip drivers/pci/onboard
* device pci x.0 on end
* register "rom_address" = "0xfff80000"
* end
* 2. Reduce the size of your normal (or fallback) image, by adding the
* following lines to your target Config.lb, after romimage "normal"
* # 48K for SCSI FW or ATI ROM
* option CONFIG_ROM_SIZE = 512*1024-48*1024
* 3. Create your vgabios.bin, for example using awardeco and put it in the
* directory of your target Config.lb. You can also read an option rom from
* a running system, but this is unreliable, as some option roms are changed
* during execution:
* # dd if=/dev/mem of=atix.rom skip=1536 count=96
* 4. After you built coreboot.rom, attach the option rom to your coreboot
* image:
* # cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > coreboot.rom
*
* Alternatively you can use the following script "nsxv" to build your image
* Usage:
* # ./nsxv s2850
*
* #!/bin/bash
* MBVENDOR=tyan
* MBMODEL=$1
* LBROOT=/home/yhlu/xx/xx
*
* echo $1
* date
*
* cd "$LBROOT/freebios2/targets"
* rm -rf "$MBVENDOR/$MBMODEL/$MBMODEL"
* ./buildtarget "$MBVENDOR/$MBMODEL" &> "$LBROOT/x_b.txt"
* cd "$MBVENDOR/$MBMODEL/$MBMODEL"
* #make clean
* eval make &> "$LBROOT/x_m.txt"
* if [ $? -eq 0 ]; then
* echo "ok."
* else
* echo "FAILED! Log excerpt:"
* tail -n 15 "$LBROOT/x_m.txt"
* exit
* fi
* cat ../atix.rom ./normal/coreboot.rom ./fallback/coreboot.rom > "$LBROOT/rom/"$MBMODEL"_coreboot.rom"
* cp -f "$LBROOT/rom/"$MBMODEL"_coreboot.rom" /home/yhlu/
*
* date
*
*/
static void onboard_enable(device_t dev)
{
struct drivers_pci_onboard_config *conf;
conf = dev->chip_info;
dev->rom_address = conf->rom_address;
}
struct chip_operations drivers_pci_onboard_ops = {
CHIP_NAME("Onboard PCI")
.enable_dev = onboard_enable,
};

1
src/include/device/device.h
View File

@@ -70,7 +70,6 @@ struct device {
unsigned int enabled : 1; /* set if we should enable the device */ unsigned int enabled : 1; /* set if we should enable the device */
unsigned int initialized : 1; /* set if we have initialized the device */ unsigned int initialized : 1; /* set if we have initialized the device */
unsigned int on_mainboard : 1; unsigned int on_mainboard : 1;
unsigned long rom_address;
u8 command; u8 command;

4
src/mainboard/amd/dbm690t/Config.lb
View File

@@ -155,9 +155,7 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/rs690 chip southbridge/amd/rs690
device pci 0.0 on end # HT 0x7910 device pci 0.0 on end # HT 0x7910
device pci 1.0 on # Internal Graphics P2P bridge 0x7912 device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F
device pci 5.0 on end # Internal Graphics 0x791F
end
end end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
device pci 3.0 off end # PCIE P2P bridge 0x791b device pci 3.0 off end # PCIE P2P bridge 0x791b

4
src/mainboard/amd/dbm690t/devicetree.cb
View File

@@ -20,9 +20,7 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/rs690 chip southbridge/amd/rs690
device pci 0.0 on end # HT 0x7910 device pci 0.0 on end # HT 0x7910
device pci 1.0 on # Internal Graphics P2P bridge 0x7912 device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F
device pci 5.0 on end # Internal Graphics 0x791F
end
end end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
device pci 3.0 off end # PCIE P2P bridge 0x791b device pci 3.0 off end # PCIE P2P bridge 0x791b

4
src/mainboard/amd/pistachio/Config.lb
View File

@@ -156,9 +156,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.0 on end # HT 0x7910 device pci 0.0 on end # HT 0x7910
# device pci 0.1 off end # CLK # device pci 0.1 off end # CLK
device pci 1.0 on # Internal Graphics P2P bridge 0x7912 device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F
device pci 5.0 on end # Internal Graphics 0x791F
end
end end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
device pci 3.0 off end # PCIE P2P bridge 0x791b device pci 3.0 off end # PCIE P2P bridge 0x791b

4
src/mainboard/amd/pistachio/devicetree.cb
View File

@@ -21,9 +21,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.0 on end # HT 0x7910 device pci 0.0 on end # HT 0x7910
# device pci 0.1 off end # CLK # device pci 0.1 off end # CLK
device pci 1.0 on # Internal Graphics P2P bridge 0x7912 device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F
device pci 5.0 on end # Internal Graphics 0x791F
end
end end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
device pci 3.0 off end # PCIE P2P bridge 0x791b device pci 3.0 off end # PCIE P2P bridge 0x791b

4
src/mainboard/arima/hdama/Config.lb
View File

@@ -177,9 +177,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end # USB1 device pci 0.1 on end # USB1
device pci 0.2 off end # USB 2.0 device pci 0.2 off end # USB 2.0
device pci 1.0 off end # LAN device pci 1.0 off end # LAN
chip drivers/pci/onboard device pci 6.0 on end # ATI Rage XL
device pci 6.0 on end # ATI Rage XL
end
## PCI Slot 5 (correct?) ## PCI Slot 5 (correct?)
#chip drivers/generic/generic #chip drivers/generic/generic
# device pci 5.0 on # device pci 5.0 on

4
src/mainboard/arima/hdama/devicetree.cb
View File

@@ -73,9 +73,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end # USB1 device pci 0.1 on end # USB1
device pci 0.2 off end # USB 2.0 device pci 0.2 off end # USB 2.0
device pci 1.0 off end # LAN device pci 1.0 off end # LAN
chip drivers/pci/onboard device pci 6.0 on end # ATI Rage XL
device pci 6.0 on end # ATI Rage XL
end
## PCI Slot 5 (correct?) ## PCI Slot 5 (correct?)
#chip drivers/generic/generic #chip drivers/generic/generic
# device pci 5.0 on # device pci 5.0 on

4
src/mainboard/artecgroup/dbe61/realmode/chip.h
View File

@@ -1,10 +1,6 @@
#ifndef PCI_REALMODE_H #ifndef PCI_REALMODE_H
#define PCI_REALMODE_H #define PCI_REALMODE_H
struct drivers_pci_realmode_config
{
unsigned long rom_address;
};
//struct chip_operations; //struct chip_operations;
extern struct chip_operations drivers_pci_realmode_ops; extern struct chip_operations drivers_pci_realmode_ops;

32
src/mainboard/artecgroup/dbe61/realmode/vgabios.c
View File

@@ -74,36 +74,6 @@
emulator to successfully run this bios. emulator to successfully run this bios.
*/ */
/*
Modified to be an universal driver for loading VGA ROMs.
Aug 2006, anti.sullin@artecdesign.ee, Artec Design
USAGE:
define in your motherboard Config.lb file in device hierarchy
around the VGA pci device realmode chip and define its rom address.
Rom address is read from Config.lb, this rom is then copied to 0xC000 and then excecuted
chip drivers/pci/realmode
device pci 1.1 on end # VGA
register "rom_address" = "0xfffc0000" # at the beginning of 256k
end
then, chip enable is called at this list first traversal, and this sets
up device's init callback. Device init is called during last list traversal and
so, other hw should be already initialized to run vga bios successfully.
*/
/* Declare a temporary global descriptor table - necessary because the /* Declare a temporary global descriptor table - necessary because the
Core part of the bios no longer sets up any 16 bit segments */ Core part of the bios no longer sets up any 16 bit segments */
__asm__ ( __asm__ (
@@ -918,8 +888,6 @@ static void vga_init(device_t dev)
// code to make vga init go through the emulator - as of yet this does not workfor the epia-m // code to make vga init go through the emulator - as of yet this does not workfor the epia-m
dev->on_mainboard=1; dev->on_mainboard=1;
dev->rom_address = (void *)cfg->rom_address;
pci_dev_init(dev); pci_dev_init(dev);
// code to make vga init run in real mode - does work but against the current coreboot philosophy // code to make vga init run in real mode - does work but against the current coreboot philosophy

5
src/mainboard/asi/mb_5blmp/Config.lb
View File

@@ -135,11 +135,6 @@ chip northbridge/amd/gx1 # Northbridge
device pci 12.2 on end # IDE device pci 12.2 on end # IDE
device pci 12.3 on end # Audio device pci 12.3 on end # Audio
device pci 12.4 on end # VGA (onboard) device pci 12.4 on end # VGA (onboard)
# device pci 12.4 on # VGA (onboard)
# chip drivers/pci/onboard
# device pci 12.4 on end
# end
# end
device pci 13.0 on end # USB device pci 13.0 on end # USB
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "ide1_enable" = "1" register "ide1_enable" = "1"

5
src/mainboard/asi/mb_5blmp/devicetree.cb
View File

@@ -37,11 +37,6 @@ chip northbridge/amd/gx1 # Northbridge
device pci 12.2 on end # IDE device pci 12.2 on end # IDE
device pci 12.3 on end # Audio device pci 12.3 on end # Audio
device pci 12.4 on end # VGA (onboard) device pci 12.4 on end # VGA (onboard)
# device pci 12.4 on # VGA (onboard)
# chip drivers/pci/onboard
# device pci 12.4 on end
# end
# end
device pci 13.0 on end # USB device pci 13.0 on end # USB
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "ide1_enable" = "1" register "ide1_enable" = "1"

4
src/mainboard/asus/mew-vm/Config.lb
View File

@@ -97,18 +97,14 @@ chip northbridge/intel/i82810
device pci_domain 0 on device pci_domain 0 on
device pci 0.0 on end # Host bridge device pci 0.0 on end # Host bridge
device pci 1.0 on # Onboard Video device pci 1.0 on # Onboard Video
#chip drivers/pci/onboard
# device pci 1.0 on end # device pci 1.0 on end
#end
end end
chip southbridge/intel/i82801xx # Southbridge chip southbridge/intel/i82801xx # Southbridge
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "ide1_enable" = "1" register "ide1_enable" = "1"
device pci 1e.0 on # PCI Bridge device pci 1e.0 on # PCI Bridge
#chip drivers/pci/onboard
# device pci 1.0 on end # device pci 1.0 on end
#end
end end
device pci 1f.0 on # ISA/LPC? Bridge device pci 1f.0 on # ISA/LPC? Bridge
chip superio/smsc/lpc47b272 chip superio/smsc/lpc47b272

4
src/mainboard/asus/mew-vm/devicetree.cb
View File

@@ -2,18 +2,14 @@ chip northbridge/intel/i82810
device pci_domain 0 on device pci_domain 0 on
device pci 0.0 on end # Host bridge device pci 0.0 on end # Host bridge
device pci 1.0 on # Onboard Video device pci 1.0 on # Onboard Video
#chip drivers/pci/onboard
# device pci 1.0 on end # device pci 1.0 on end
#end
end end
chip southbridge/intel/i82801xx # Southbridge chip southbridge/intel/i82801xx # Southbridge
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "ide1_enable" = "1" register "ide1_enable" = "1"
device pci 1e.0 on # PCI Bridge device pci 1e.0 on # PCI Bridge
#chip drivers/pci/onboard
# device pci 1.0 on end # device pci 1.0 on end
#end
end end
device pci 1f.0 on # ISA/LPC? Bridge device pci 1f.0 on # ISA/LPC? Bridge
chip superio/smsc/lpc47b272 chip superio/smsc/lpc47b272

15
src/mainboard/broadcom/blast/Config.lb
View File

@@ -207,21 +207,8 @@ chip northbridge/amd/amdk8/root_complex
device pci 2.0 on end # USB 0x0223 device pci 2.0 on end # USB 0x0223
device pci 2.1 on end # USB device pci 2.1 on end # USB
device pci 2.2 on end # USB device pci 2.2 on end # USB
#when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), device pci 4.0 on end # it is in bcm5785_0 bus
chip drivers/pci/onboard
device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
# if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
end
end end
#when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
# chip drivers/pci/onboard
# device pci 0.0 on end # fake, will be disabled
# end
# chip drivers/pci/onboard
# device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
# end
end # device pci 18.0 end # device pci 18.0
device pci 18.0 on end device pci 18.0 on end

15
src/mainboard/broadcom/blast/devicetree.cb
View File

@@ -105,21 +105,8 @@ chip northbridge/amd/amdk8/root_complex
device pci 2.0 on end # USB 0x0223 device pci 2.0 on end # USB 0x0223
device pci 2.1 on end # USB device pci 2.1 on end # USB
device pci 2.2 on end # USB device pci 2.2 on end # USB
#when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), device pci 4.0 on end # it is in bcm5785_0 bus
chip drivers/pci/onboard
device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
# if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
end
end end
#when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
# chip drivers/pci/onboard
# device pci 0.0 on end # fake, will be disabled
# end
# chip drivers/pci/onboard
# device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
# end
end # device pci 18.0 end # device pci 18.0
device pci 18.0 on end device pci 18.0 on end

9
src/mainboard/digitallogic/msm586seg/Config.lb
View File

@@ -102,13 +102,8 @@ config chip.h
chip cpu/amd/sc520 chip cpu/amd/sc520
device pci_domain 0 on device pci_domain 0 on
device pci 0.0 on end device pci 0.0 on end
device pci 12.0 on end # enet
chip drivers/pci/onboard device pci 14.0 on end # 69000
device pci 12.0 on end # enet
end
chip drivers/pci/onboard
device pci 14.0 on end # 69000
end
# register "com1" = "{1}" # register "com1" = "{1}"
# register "com1" = "{1, 0, 0x3f8, 4}" # register "com1" = "{1, 0, 0x3f8, 4}"
end end

9
src/mainboard/digitallogic/msm586seg/devicetree.cb
View File

@@ -1,13 +1,8 @@
chip cpu/amd/sc520 chip cpu/amd/sc520
device pci_domain 0 on device pci_domain 0 on
device pci 0.0 on end device pci 0.0 on end
device pci 12.0 on end # enet
chip drivers/pci/onboard device pci 14.0 on end # 69000
device pci 12.0 on end # enet
end
chip drivers/pci/onboard
device pci 14.0 on end # 69000
end
# register "com1" = "{1}" # register "com1" = "{1}"
# register "com1" = "{1, 0, 0x3f8, 4}" # register "com1" = "{1, 0, 0x3f8, 4}"
end end

1
src/mainboard/emulation/qemu-x86/mainboard.c
View File

@@ -16,7 +16,6 @@ static void qemu_init(device_t dev)
* force coreboot to use it. * force coreboot to use it.
*/ */
dev->on_mainboard = 1; dev->on_mainboard = 1;
dev->rom_address = 0xc0000;
/* Now do the usual initialization */ /* Now do the usual initialization */
pci_dev_init(dev); pci_dev_init(dev);

2
src/mainboard/gigabyte/ga_2761gxdk/Config.lb
View File

@@ -178,9 +178,7 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/sis/sis966 chip southbridge/sis/sis966
device pci 0.0 on end # Northbridge device pci 0.0 on end # Northbridge
device pci 1.0 on # AGP bridge device pci 1.0 on # AGP bridge
chip drivers/pci/onboard # Integrated VGA
device pci 0.0 on end device pci 0.0 on end
end
end end
device pci 2.0 on # LPC device pci 2.0 on # LPC
chip superio/ite/it8716f chip superio/ite/it8716f

2
src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb
View File

@@ -11,9 +11,7 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/sis/sis966 chip southbridge/sis/sis966
device pci 0.0 on end # Northbridge device pci 0.0 on end # Northbridge
device pci 1.0 on # AGP bridge device pci 1.0 on # AGP bridge
chip drivers/pci/onboard # Integrated VGA
device pci 0.0 on end device pci 0.0 on end
end
end end
device pci 2.0 on # LPC device pci 2.0 on # LPC
chip superio/ite/it8716f chip superio/ite/it8716f

9
src/mainboard/hp/dl145_g3/Config.lb
View File

@@ -195,15 +195,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 2.1 on end # USB device pci 2.1 on end # USB
device pci 2.2 on end # USB device pci 2.2 on end # USB
device pci 3.0 on end # VGA device pci 3.0 on end # VGA
#bx_a013+ start
#chip drivers/pci/onboard #SATA2
# device pci 5.0 on end
# device pci 5.1 on end
# device pci 5.2 on end
# device pci 5.3 on end
#end
#bx_a013+ end
end end
end end
device pci 18.0 on end device pci 18.0 on end

9
src/mainboard/hp/dl145_g3/devicetree.cb
View File

@@ -72,15 +72,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 2.1 on end # USB device pci 2.1 on end # USB
device pci 2.2 on end # USB device pci 2.2 on end # USB
device pci 3.0 on end # VGA device pci 3.0 on end # VGA
#bx_a013+ start
#chip drivers/pci/onboard #SATA2
# device pci 5.0 on end
# device pci 5.1 on end
# device pci 5.2 on end
# device pci 5.3 on end
#end
#bx_a013+ end
end end
end end
device pci 18.0 on end device pci 18.0 on end

4
src/mainboard/hp/e_vectra_p2706t/Config.lb
View File

@@ -76,9 +76,7 @@ chip northbridge/intel/i82810 # Northbridge
end end
device pci_domain 0 on device pci_domain 0 on
device pci 0.0 on end # Host bridge device pci 0.0 on end # Host bridge
chip drivers/pci/onboard # Onboard VGA device pci 1.0 on end # Onboard VGA
device pci 1.0 on end
end
chip southbridge/intel/i82801xx # Southbridge chip southbridge/intel/i82801xx # Southbridge
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "ide1_enable" = "1" register "ide1_enable" = "1"

4
src/mainboard/hp/e_vectra_p2706t/devicetree.cb
View File

@@ -7,9 +7,7 @@ chip northbridge/intel/i82810 # Northbridge
end end
device pci_domain 0 on device pci_domain 0 on
device pci 0.0 on end # Host bridge device pci 0.0 on end # Host bridge
chip drivers/pci/onboard # Onboard VGA device pci 1.0 on end # Onboard VGA
device pci 1.0 on end
end
chip southbridge/intel/i82801xx # Southbridge chip southbridge/intel/i82801xx # Southbridge
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "ide1_enable" = "1" register "ide1_enable" = "1"

4
src/mainboard/ibm/e326/Config.lb
View File

@@ -125,9 +125,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end device pci 0.1 on end
device pci 0.2 on end device pci 0.2 on end
device pci 1.0 off end device pci 1.0 off end
chip drivers/pci/onboard device pci 5.0 on end # ATI Rage XL
device pci 5.0 on end # ATI Rage XL
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/nsc/pc87366 chip superio/nsc/pc87366

4
src/mainboard/ibm/e326/devicetree.cb
View File

@@ -21,9 +21,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end device pci 0.1 on end
device pci 0.2 on end device pci 0.2 on end
device pci 1.0 off end device pci 1.0 off end
chip drivers/pci/onboard device pci 5.0 on end # ATI Rage XL
device pci 5.0 on end # ATI Rage XL
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/nsc/pc87366 chip superio/nsc/pc87366

4
src/mainboard/intel/d945gclf/Config.lb
View File

@@ -150,9 +150,7 @@ chip northbridge/intel/i945
device pci_domain 0 on device pci_domain 0 on
device pci 00.0 on end # host bridge device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port device pci 01.0 off end # i945 PCIe root port
chip drivers/pci/onboard device pci 02.0 on end # vga controller
device pci 02.0 on end # vga controller
end
device pci 02.1 on end # display controller device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx chip southbridge/intel/i82801gx

4
src/mainboard/intel/d945gclf/devicetree.cb
View File

@@ -28,9 +28,7 @@ chip northbridge/intel/i945
device pci_domain 0 on device pci_domain 0 on
device pci 00.0 on end # host bridge device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port device pci 01.0 off end # i945 PCIe root port
chip drivers/pci/onboard device pci 02.0 on end # vga controller
device pci 02.0 on end # vga controller
end
device pci 02.1 on end # display controller device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx chip southbridge/intel/i82801gx

4
src/mainboard/intel/xe7501devkit/Config.lb
View File

@@ -127,9 +127,7 @@ chip northbridge/intel/e7501
device pci 1d.1 off end # USB (not populated) device pci 1d.1 off end # USB (not populated)
device pci 1d.2 off end # USB (not populated) device pci 1d.2 off end # USB (not populated)
device pci 1e.0 on # Hub to PCI bridge device pci 1e.0 on # Hub to PCI bridge
chip drivers/pci/onboard # VGA ROM device pci 0.0 on end
device pci 0.0 on end
end
end end
device pci 1f.0 on # LPC bridge device pci 1f.0 on # LPC bridge
chip superio/smsc/lpc47b272 chip superio/smsc/lpc47b272

4
src/mainboard/intel/xe7501devkit/devicetree.cb
View File

@@ -25,9 +25,7 @@ chip northbridge/intel/e7501
device pci 1d.1 off end # USB (not populated) device pci 1d.1 off end # USB (not populated)
device pci 1d.2 off end # USB (not populated) device pci 1d.2 off end # USB (not populated)
device pci 1e.0 on # Hub to PCI bridge device pci 1e.0 on # Hub to PCI bridge
chip drivers/pci/onboard # VGA ROM device pci 0.0 on end
device pci 0.0 on end
end
end end
device pci 1f.0 on # LPC bridge device pci 1f.0 on # LPC bridge
chip superio/smsc/lpc47b272 chip superio/smsc/lpc47b272

3
src/mainboard/iwill/dk8_htx/Config.lb
View File

@@ -232,9 +232,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end device pci 0.1 on end
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
#chip drivers/pci/onboard
# device pci 6.0 on end
#end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

3
src/mainboard/iwill/dk8_htx/devicetree.cb
View File

@@ -24,9 +24,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end device pci 0.1 on end
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
#chip drivers/pci/onboard
# device pci 6.0 on end
#end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

4
src/mainboard/kontron/986lcd-m/Config.lb
View File

@@ -153,9 +153,7 @@ chip northbridge/intel/i945
device pci 00.0 on end # host bridge device pci 00.0 on end # host bridge
# autodetect 0:1.0 because it might or might not be there. # autodetect 0:1.0 because it might or might not be there.
# device pci 01.0 off end # i945 PCIe root port # device pci 01.0 off end # i945 PCIe root port
chip drivers/pci/onboard device pci 02.0 on end # vga controller
device pci 02.0 on end # vga controller
end
device pci 02.1 on end # display controller device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx chip southbridge/intel/i82801gx

4
src/mainboard/kontron/986lcd-m/devicetree.cb
View File

@@ -9,9 +9,7 @@ chip northbridge/intel/i945
device pci_domain 0 on device pci_domain 0 on
device pci 00.0 on end # host bridge device pci 00.0 on end # host bridge
device pci 01.0 off end # i945 PCIe root port device pci 01.0 off end # i945 PCIe root port
chip drivers/pci/onboard device pci 02.0 on end # vga controller
device pci 02.0 on end # vga controller
end
device pci 02.1 on end # display controller device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx chip southbridge/intel/i82801gx

4
src/mainboard/kontron/kt690/Config.lb
View File

@@ -155,9 +155,7 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/rs690 chip southbridge/amd/rs690
device pci 0.0 on end # HT 0x7910 device pci 0.0 on end # HT 0x7910
device pci 1.0 on # Internal Graphics P2P bridge 0x7912 device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F
device pci 5.0 on end # Internal Graphics 0x791F
end
end end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
device pci 3.0 off end # PCIE P2P bridge 0x791b device pci 3.0 off end # PCIE P2P bridge 0x791b

4
src/mainboard/kontron/kt690/devicetree.cb
View File

@@ -20,9 +20,7 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/rs690 chip southbridge/amd/rs690
device pci 0.0 on end # HT 0x7910 device pci 0.0 on end # HT 0x7910
device pci 1.0 on # Internal Graphics P2P bridge 0x7912 device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F
device pci 5.0 on end # Internal Graphics 0x791F
end
end end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
device pci 3.0 off end # PCIE P2P bridge 0x791b device pci 3.0 off end # PCIE P2P bridge 0x791b

4
src/mainboard/mitac/6513wu/Config.lb
View File

@@ -80,9 +80,7 @@ chip northbridge/intel/i82810 # Northbridge
end end
device pci_domain 0 on # PCI domain device pci_domain 0 on # PCI domain
device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
chip drivers/pci/onboard device pci 1.0 on end
device pci 1.0 on end
end
chip southbridge/intel/i82801xx # Southbridge chip southbridge/intel/i82801xx # Southbridge
register "pirqa_routing" = "0x03" register "pirqa_routing" = "0x03"
register "pirqb_routing" = "0x05" register "pirqb_routing" = "0x05"

4
src/mainboard/mitac/6513wu/devicetree.cb
View File

@@ -26,9 +26,7 @@ chip northbridge/intel/i82810 # Northbridge
end end
device pci_domain 0 on # PCI domain device pci_domain 0 on # PCI domain
device pci 0.0 on end # Graphics Memory Controller Hub (GMCH) device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
chip drivers/pci/onboard device pci 1.0 on end
device pci 1.0 on end
end
chip southbridge/intel/i82801xx # Southbridge chip southbridge/intel/i82801xx # Southbridge
register "pirqa_routing" = "0x03" register "pirqa_routing" = "0x03"
register "pirqb_routing" = "0x05" register "pirqb_routing" = "0x05"

4
src/mainboard/msi/ms6178/Config.lb
View File

@@ -75,9 +75,7 @@ chip northbridge/intel/i82810 # Northbridge
end end
device pci_domain 0 on device pci_domain 0 on
device pci 0.0 on end # Host bridge device pci 0.0 on end # Host bridge
chip drivers/pci/onboard # Onboard VGA device pci 1.0 on end # Onboard VGA
device pci 1.0 on end
end
chip southbridge/intel/i82801xx # Southbridge chip southbridge/intel/i82801xx # Southbridge
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "ide1_enable" = "1" register "ide1_enable" = "1"

4
src/mainboard/msi/ms6178/devicetree.cb
View File

@@ -26,9 +26,7 @@ chip northbridge/intel/i82810 # Northbridge
end end
device pci_domain 0 on device pci_domain 0 on
device pci 0.0 on end # Host bridge device pci 0.0 on end # Host bridge
chip drivers/pci/onboard # Onboard VGA device pci 1.0 on end # Onboard VGA
device pci 1.0 on end
end
chip southbridge/intel/i82801xx # Southbridge chip southbridge/intel/i82801xx # Southbridge
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "ide1_enable" = "1" register "ide1_enable" = "1"

23
src/mainboard/msi/ms9185/Config.lb
View File

@@ -207,29 +207,8 @@ chip northbridge/amd/amdk8/root_complex
device pci 2.0 on end # USB 0x0223 device pci 2.0 on end # USB 0x0223
device pci 2.1 on end # USB device pci 2.1 on end # USB
device pci 2.2 on end # USB device pci 2.2 on end # USB
#when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), device pci 3.0 on end # it is in bcm5785_0 bus
chip drivers/pci/onboard
device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
# if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3
end
#bx_a013+ start
#chip drivers/pci/onboard #SATA2
# device pci 5.0 on end
# device pci 5.1 on end
# device pci 5.2 on end
# device pci 5.3 on end
#end
#bx_a013+ end
end end
#when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
# chip drivers/pci/onboard
# device pci 0.0 on end # fake, will be disabled
# end
# chip drivers/pci/onboard
# device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
# end
end # device pci 18.0 end # device pci 18.0
device pci 18.1 on end device pci 18.1 on end
device pci 18.2 on end device pci 18.2 on end

23
src/mainboard/msi/ms9185/devicetree.cb
View File

@@ -73,29 +73,8 @@ chip northbridge/amd/amdk8/root_complex
device pci 2.0 on end # USB 0x0223 device pci 2.0 on end # USB 0x0223
device pci 2.1 on end # USB device pci 2.1 on end # USB
device pci 2.2 on end # USB device pci 2.2 on end # USB
#when CONFIG_HT_CHAIN_END_UNITID_BASE (0,1) < CONFIG_HT_CHAIN_UNITID_BASE (6,,,,), device pci 3.0 on end # it is in bcm5785_0 bus
chip drivers/pci/onboard
device pci 3.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
# if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 4, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 3
end
#bx_a013+ start
#chip drivers/pci/onboard #SATA2
# device pci 5.0 on end
# device pci 5.1 on end
# device pci 5.2 on end
# device pci 5.3 on end
#end
#bx_a013+ end
end end
#when CONFIG_HT_CHAIN_END_UNITID_BASE > CONFIG_HT_CHAIN_UNITID_BASE (6, ,,,,)
# chip drivers/pci/onboard
# device pci 0.0 on end # fake, will be disabled
# end
# chip drivers/pci/onboard
# device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
# end
end # device pci 18.0 end # device pci 18.0
device pci 18.1 on end device pci 18.1 on end
device pci 18.2 on end device pci 18.2 on end

14
src/mainboard/msi/ms9282/Config.lb
View File

@@ -278,27 +278,21 @@ chip northbridge/amd/amdk8/root_complex
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on #P2P device pci 6.0 on #P2P
chip drivers/pci/onboard device pci 4.0 on end
device pci 4.0 on end
end
end # P2P end # P2P
device pci 7.0 on end # reserve device pci 7.0 on end # reserve
device pci 8.0 on end # MAC0 device pci 8.0 on end # MAC0
device pci 9.0 on end # MAC1 device pci 9.0 on end # MAC1
device pci a.0 on device pci a.0 on
device pci 0.0 on device pci 0.0 on
chip drivers/pci/onboard device pci 4.0 on end #pci_E lan1
device pci 4.0 on end #pci_E lan1 device pci 4.1 on end #pci_E lan2
device pci 4.1 on end #pci_E lan2
end
end end
end # 0x376 end # 0x376
device pci b.0 on end # PCI E 0x374 device pci b.0 on end # PCI E 0x374
device pci c.0 on end device pci c.0 on end
device pci d.0 on #SAS device pci d.0 on #SAS
chip drivers/pci/onboard device pci 0.0 on end
device pci 0.0 on end
end
end # PCI E 1 0x378 end # PCI E 1 0x378
device pci e.0 on end # PCI E 0 0x375 device pci e.0 on end # PCI E 0 0x375
device pci f.0 on end #PCI E 0x377 pci_E slot device pci f.0 on end #PCI E 0x377 pci_E slot

14
src/mainboard/msi/ms9282/devicetree.cb
View File

@@ -137,27 +137,21 @@ chip northbridge/amd/amdk8/root_complex
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on #P2P device pci 6.0 on #P2P
chip drivers/pci/onboard device pci 4.0 on end
device pci 4.0 on end
end
end # P2P end # P2P
device pci 7.0 on end # reserve device pci 7.0 on end # reserve
device pci 8.0 on end # MAC0 device pci 8.0 on end # MAC0
device pci 9.0 on end # MAC1 device pci 9.0 on end # MAC1
device pci a.0 on device pci a.0 on
device pci 0.0 on device pci 0.0 on
chip drivers/pci/onboard device pci 4.0 on end #pci_E lan1
device pci 4.0 on end #pci_E lan1 device pci 4.1 on end #pci_E lan2
device pci 4.1 on end #pci_E lan2
end
end end
end # 0x376 end # 0x376
device pci b.0 on end # PCI E 0x374 device pci b.0 on end # PCI E 0x374
device pci c.0 on end device pci c.0 on end
device pci d.0 on #SAS device pci d.0 on #SAS
chip drivers/pci/onboard device pci 0.0 on end
device pci 0.0 on end
end
end # PCI E 1 0x378 end # PCI E 1 0x378
device pci e.0 on end # PCI E 0 0x375 device pci e.0 on end # PCI E 0 0x375
device pci f.0 on end #PCI E 0x377 pci_E slot device pci f.0 on end #PCI E 0x377 pci_E slot

6
src/mainboard/nec/powermate2000/Config.lb
View File

@@ -75,11 +75,7 @@ chip northbridge/intel/i82810 # Northbridge
end end
device pci_domain 0 on device pci_domain 0 on
device pci 0.0 on end # Host bridge device pci 0.0 on end # Host bridge
device pci 1.0 off # Onboard video device pci 1.0 off end # Onboard video
# chip drivers/pci/onboard
# device pci 1.0 on end
# end
end
chip southbridge/intel/i82801xx # Southbridge chip southbridge/intel/i82801xx # Southbridge
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "ide1_enable" = "1" register "ide1_enable" = "1"

6
src/mainboard/nec/powermate2000/devicetree.cb
View File

@@ -6,11 +6,7 @@ chip northbridge/intel/i82810 # Northbridge
end end
device pci_domain 0 on device pci_domain 0 on
device pci 0.0 on end # Host bridge device pci 0.0 on end # Host bridge
device pci 1.0 off # Onboard video device pci 1.0 off end # Onboard video
# chip drivers/pci/onboard
# device pci 1.0 on end
# end
end
chip southbridge/intel/i82801xx # Southbridge chip southbridge/intel/i82801xx # Southbridge
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "ide1_enable" = "1" register "ide1_enable" = "1"

2
src/mainboard/newisys/khepri/Config.lb
View File

@@ -98,8 +98,6 @@ end
config chip.h config chip.h
# FIXME: ROM for onboard VGA
chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on device apic_cluster 0 on
chip cpu/amd/socket_940 chip cpu/amd/socket_940

4
src/mainboard/rca/rm4100/Config.lb
View File

@@ -75,9 +75,7 @@ config chip.h
chip northbridge/intel/i82830 # Northbridge chip northbridge/intel/i82830 # Northbridge
device pci_domain 0 on # PCI domain device pci_domain 0 on # PCI domain
device pci 0.0 on end # Host bridge device pci 0.0 on end # Host bridge
chip drivers/pci/onboard # Onboard VGA device pci 2.0 on end # VGA (Intel 82830 CGC)
device pci 2.0 on end # VGA (Intel 82830 CGC)
end
chip southbridge/intel/i82801xx # Southbridge chip southbridge/intel/i82801xx # Southbridge
register "pirqa_routing" = "0x05" register "pirqa_routing" = "0x05"
register "pirqb_routing" = "0x06" register "pirqb_routing" = "0x06"

4
src/mainboard/rca/rm4100/devicetree.cb
View File

@@ -1,9 +1,7 @@
chip northbridge/intel/i82830 # Northbridge chip northbridge/intel/i82830 # Northbridge
device pci_domain 0 on # PCI domain device pci_domain 0 on # PCI domain
device pci 0.0 on end # Host bridge device pci 0.0 on end # Host bridge
chip drivers/pci/onboard # Onboard VGA device pci 2.0 on end # VGA (Intel 82830 CGC)
device pci 2.0 on end # VGA (Intel 82830 CGC)
end
chip southbridge/intel/i82801xx # Southbridge chip southbridge/intel/i82801xx # Southbridge
register "pirqa_routing" = "0x05" register "pirqa_routing" = "0x05"
register "pirqb_routing" = "0x06" register "pirqb_routing" = "0x06"

3
src/mainboard/sunw/ultra40/Config.lb
View File

@@ -210,8 +210,6 @@ chip northbridge/amd/amdk8/root_complex
register "ide1_enable" = "1" register "ide1_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
# register "nic_rom_address" = "0xfff80000" # 64k
# register "raid_rom_address" = "0xfff90000"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_addr" = "0x51"
end end
@@ -243,7 +241,6 @@ chip northbridge/amd/amdk8/root_complex
device pci c.0 off end # PCI E 2 device pci c.0 off end # PCI E 2
device pci d.0 off end # PCI E 1 device pci d.0 off end # PCI E 1
device pci e.0 on end # PCI E 0 device pci e.0 on end # PCI E 0
# register "nic_rom_address" = "0xfff80000" # 64k
register "mac_eeprom_smbus" = "3" register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_addr" = "0x51"
end end

3
src/mainboard/sunw/ultra40/devicetree.cb
View File

@@ -106,8 +106,6 @@ chip northbridge/amd/amdk8/root_complex
register "ide1_enable" = "1" register "ide1_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
# register "nic_rom_address" = "0xfff80000" # 64k
# register "raid_rom_address" = "0xfff90000"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_addr" = "0x51"
end end
@@ -139,7 +137,6 @@ chip northbridge/amd/amdk8/root_complex
device pci c.0 off end # PCI E 2 device pci c.0 off end # PCI E 2
device pci d.0 off end # PCI E 1 device pci d.0 off end # PCI E 1
device pci e.0 on end # PCI E 0 device pci e.0 on end # PCI E 0
# register "nic_rom_address" = "0xfff80000" # 64k
register "mac_eeprom_smbus" = "3" register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_addr" = "0x51"
end end

4
src/mainboard/supermicro/h8dme/Config.lb
View File

@@ -254,9 +254,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on # PCI device pci 6.0 on # PCI
chip drivers/pci/onboard device pci 6.0 on end
device pci 6.0 on end
end
end end
device pci 6.1 on end # AZA device pci 6.1 on end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC

4
src/mainboard/supermicro/h8dme/devicetree.cb
View File

@@ -92,9 +92,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on # PCI device pci 6.0 on # PCI
chip drivers/pci/onboard device pci 6.0 on end
device pci 6.0 on end
end
end end
device pci 6.1 on end # AZA device pci 6.1 on end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC

4
src/mainboard/supermicro/h8dmr/Config.lb
View File

@@ -276,9 +276,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on # PCI device pci 6.0 on # PCI
chip drivers/pci/onboard device pci 6.0 on end
device pci 6.0 on end
end
end end
device pci 6.1 on end # AZA device pci 6.1 on end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC

4
src/mainboard/supermicro/h8dmr/devicetree.cb
View File

@@ -112,9 +112,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on # PCI device pci 6.0 on # PCI
chip drivers/pci/onboard device pci 6.0 on end
device pci 6.0 on end
end
end end
device pci 6.1 on end # AZA device pci 6.1 on end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC

4
src/mainboard/supermicro/h8dmr_fam10/Config.lb
View File

@@ -280,9 +280,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on # PCI device pci 6.0 on # PCI
chip drivers/pci/onboard device pci 6.0 on end
device pci 6.0 on end
end
end end
device pci 6.1 on end # AZA device pci 6.1 on end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC

4
src/mainboard/supermicro/h8dmr_fam10/devicetree.cb
View File

@@ -114,9 +114,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on # PCI device pci 6.0 on # PCI
chip drivers/pci/onboard device pci 6.0 on end
device pci 6.0 on end
end
end end
device pci 6.1 on end # AZA device pci 6.1 on end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC

4
src/mainboard/technexion/tim5690/Config.lb
View File

@@ -155,9 +155,7 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/rs690 chip southbridge/amd/rs690
device pci 0.0 on end # HT 0x7910 device pci 0.0 on end # HT 0x7910
device pci 1.0 on # Internal Graphics P2P bridge 0x7912 device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F
device pci 5.0 on end # Internal Graphics 0x791F
end
end end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
device pci 3.0 off end # PCIE P2P bridge 0x791b device pci 3.0 off end # PCIE P2P bridge 0x791b

4
src/mainboard/technexion/tim5690/devicetree.cb
View File

@@ -20,9 +20,7 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/rs690 chip southbridge/amd/rs690
device pci 0.0 on end # HT 0x7910 device pci 0.0 on end # HT 0x7910
device pci 1.0 on # Internal Graphics P2P bridge 0x7912 device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F
device pci 5.0 on end # Internal Graphics 0x791F
end
end end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
device pci 3.0 off end # PCIE P2P bridge 0x791b device pci 3.0 off end # PCIE P2P bridge 0x791b

4
src/mainboard/technexion/tim8690/Config.lb
View File

@@ -155,9 +155,7 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/rs690 chip southbridge/amd/rs690
device pci 0.0 on end # HT 0x7910 device pci 0.0 on end # HT 0x7910
device pci 1.0 on # Internal Graphics P2P bridge 0x7912 device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F
device pci 5.0 on end # Internal Graphics 0x791F
end
end end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
device pci 3.0 off end # PCIE P2P bridge 0x791b device pci 3.0 off end # PCIE P2P bridge 0x791b

4
src/mainboard/technexion/tim8690/devicetree.cb
View File

@@ -20,9 +20,7 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/rs690 chip southbridge/amd/rs690
device pci 0.0 on end # HT 0x7910 device pci 0.0 on end # HT 0x7910
device pci 1.0 on # Internal Graphics P2P bridge 0x7912 device pci 1.0 on # Internal Graphics P2P bridge 0x7912
chip drivers/pci/onboard device pci 5.0 on end # Internal Graphics 0x791F
device pci 5.0 on end # Internal Graphics 0x791F
end
end end
device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
device pci 3.0 off end # PCIE P2P bridge 0x791b device pci 3.0 off end # PCIE P2P bridge 0x791b

6
src/mainboard/technologic/ts5300/Config.lb
View File

@@ -104,12 +104,6 @@ chip cpu/amd/sc520
device pci_domain 0 on device pci_domain 0 on
device pci 0.0 on end device pci 0.0 on end
# chip drivers/pci/onboard
# device pci 12.0 on end # enet
# end
# chip drivers/pci/onboard
# device pci 14.0 on end # 69000
# end
# register "com1" = "{1}" # register "com1" = "{1}"
# register "com1" = "{1, 0, 0x3f8, 4}" # register "com1" = "{1, 0, 0x3f8, 4}"
end end

6
src/mainboard/technologic/ts5300/devicetree.cb
View File

@@ -2,12 +2,6 @@ chip cpu/amd/sc520
device pci_domain 0 on device pci_domain 0 on
device pci 0.0 on end device pci 0.0 on end
# chip drivers/pci/onboard
# device pci 12.0 on end # enet
# end
# chip drivers/pci/onboard
# device pci 14.0 on end # 69000
# end
# register "com1" = "{1}" # register "com1" = "{1}"
# register "com1" = "{1, 0, 0x3f8, 4}" # register "com1" = "{1, 0, 0x3f8, 4}"
end end

4
src/mainboard/thomson/ip1000/Config.lb
View File

@@ -75,9 +75,7 @@ config chip.h
chip northbridge/intel/i82830 # Northbridge chip northbridge/intel/i82830 # Northbridge
device pci_domain 0 on # PCI domain device pci_domain 0 on # PCI domain
device pci 0.0 on end # Host bridge device pci 0.0 on end # Host bridge
chip drivers/pci/onboard # Onboard VGA device pci 2.0 on end # VGA (Intel 82830 CGC)
device pci 2.0 on end # VGA (Intel 82830 CGC)
end
chip southbridge/intel/i82801xx # Southbridge chip southbridge/intel/i82801xx # Southbridge
register "pirqa_routing" = "0x05" register "pirqa_routing" = "0x05"
register "pirqb_routing" = "0x06" register "pirqb_routing" = "0x06"

4
src/mainboard/thomson/ip1000/devicetree.cb
View File

@@ -1,9 +1,7 @@
chip northbridge/intel/i82830 # Northbridge chip northbridge/intel/i82830 # Northbridge
device pci_domain 0 on # PCI domain device pci_domain 0 on # PCI domain
device pci 0.0 on end # Host bridge device pci 0.0 on end # Host bridge
chip drivers/pci/onboard # Onboard VGA device pci 2.0 on end # VGA (Intel 82830 CGC)
device pci 2.0 on end # VGA (Intel 82830 CGC)
end
chip southbridge/intel/i82801xx # Southbridge chip southbridge/intel/i82801xx # Southbridge
register "pirqa_routing" = "0x05" register "pirqa_routing" = "0x05"
register "pirqb_routing" = "0x06" register "pirqb_routing" = "0x06"

14
src/mainboard/tyan/s2735/Config.lb
View File

@@ -100,10 +100,8 @@ chip northbridge/intel/e7501
chip southbridge/intel/i82870 chip southbridge/intel/i82870
device pci 1c.0 on end device pci 1c.0 on end
device pci 1d.0 on device pci 1d.0 on
chip drivers/pci/onboard device pci 1.0 on end # intel lan
device pci 1.0 on end # intel lan device pci 1.1 on end
device pci 1.1 on end
end
end end
device pci 1e.0 on end device pci 1e.0 on end
device pci 1f.0 on end device pci 1f.0 on end
@@ -117,12 +115,8 @@ chip northbridge/intel/e7501
device pci 1d.3 on end device pci 1d.3 on end
device pci 1d.7 on end device pci 1d.7 on end
device pci 1e.0 on device pci 1e.0 on
chip drivers/pci/onboard device pci 1.0 on end # intel lan 10/100
device pci 1.0 on end # intel lan 10/100 device pci 2.0 on end # ati
end
chip drivers/pci/onboard
device pci 2.0 on end # ati
end
end end
device pci 1f.0 on device pci 1f.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

14
src/mainboard/tyan/s2735/devicetree.cb
View File

@@ -6,10 +6,8 @@ chip northbridge/intel/e7501
chip southbridge/intel/i82870 chip southbridge/intel/i82870
device pci 1c.0 on end device pci 1c.0 on end
device pci 1d.0 on device pci 1d.0 on
chip drivers/pci/onboard device pci 1.0 on end # intel lan
device pci 1.0 on end # intel lan device pci 1.1 on end
device pci 1.1 on end
end
end end
device pci 1e.0 on end device pci 1e.0 on end
device pci 1f.0 on end device pci 1f.0 on end
@@ -23,12 +21,8 @@ chip northbridge/intel/e7501
device pci 1d.3 on end device pci 1d.3 on end
device pci 1d.7 on end device pci 1d.7 on end
device pci 1e.0 on device pci 1e.0 on
chip drivers/pci/onboard device pci 1.0 on end # intel lan 10/100
device pci 1.0 on end # intel lan 10/100 device pci 2.0 on end # ati
end
chip drivers/pci/onboard
device pci 2.0 on end # ati
end
end end
device pci 1f.0 on device pci 1f.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

4
src/mainboard/tyan/s2850/Config.lb
View File

@@ -119,9 +119,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
#chip drivers/ati/ragexl #chip drivers/ati/ragexl
chip drivers/pci/onboard device pci b.0 on end
device pci b.0 on end
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

4
src/mainboard/tyan/s2850/devicetree.cb
View File

@@ -17,9 +17,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
#chip drivers/ati/ragexl #chip drivers/ati/ragexl
chip drivers/pci/onboard device pci b.0 on end
device pci b.0 on end
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

4
src/mainboard/tyan/s2875/Config.lb
View File

@@ -123,9 +123,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end device pci 0.1 on end
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
chip drivers/pci/onboard device pci 5.0 on end
device pci 5.0 on end
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

4
src/mainboard/tyan/s2875/devicetree.cb
View File

@@ -21,9 +21,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end device pci 0.1 on end
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
chip drivers/pci/onboard device pci 5.0 on end
device pci 5.0 on end
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

14
src/mainboard/tyan/s2880/Config.lb
View File

@@ -113,10 +113,8 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/amd8131 chip southbridge/amd/amd8131
# the on/off keyword is mandatory # the on/off keyword is mandatory
device pci 0.0 on device pci 0.0 on
chip drivers/pci/onboard device pci 9.0 on end #broadcom
device pci 9.0 on end #broadcom device pci 9.1 on end
device pci 9.1 on end
end
# chip drivers/lsi/53c1030 # chip drivers/lsi/53c1030
# device pci a.0 on end # device pci a.0 on end
# device pci a.1 on end # device pci a.1 on end
@@ -135,12 +133,8 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end device pci 0.1 on end
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
chip drivers/pci/onboard device pci 5.0 on end #some sata
device pci 5.0 on end #some sata device pci 6.0 on end #adti
end
chip drivers/pci/onboard
device pci 6.0 on end #adti
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

14
src/mainboard/tyan/s2880/devicetree.cb
View File

@@ -11,10 +11,8 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/amd8131 chip southbridge/amd/amd8131
# the on/off keyword is mandatory # the on/off keyword is mandatory
device pci 0.0 on device pci 0.0 on
chip drivers/pci/onboard device pci 9.0 on end #broadcom
device pci 9.0 on end #broadcom device pci 9.1 on end
device pci 9.1 on end
end
# chip drivers/lsi/53c1030 # chip drivers/lsi/53c1030
# device pci a.0 on end # device pci a.0 on end
# device pci a.1 on end # device pci a.1 on end
@@ -33,12 +31,8 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end device pci 0.1 on end
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
chip drivers/pci/onboard device pci 5.0 on end #some sata
device pci 5.0 on end #some sata device pci 6.0 on end #adti
end
chip drivers/pci/onboard
device pci 6.0 on end #adti
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

20
src/mainboard/tyan/s2881/Config.lb
View File

@@ -115,14 +115,10 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/amd8131 chip southbridge/amd/amd8131
# the on/off keyword is mandatory # the on/off keyword is mandatory
device pci 0.0 on device pci 0.0 on
chip drivers/pci/onboard device pci 9.0 on end # Broadcom 5704
device pci 9.0 on end # Broadcom 5704 device pci 9.1 on end
device pci 9.1 on end device pci a.0 on end # Adaptic
end device pci a.1 on end
chip drivers/pci/onboard
device pci a.0 on end # Adaptic
device pci a.1 on end
end
end end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on end device pci 1.0 on end
@@ -136,12 +132,8 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end device pci 0.1 on end
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
chip drivers/pci/onboard device pci 5.0 on end # SiI
device pci 5.0 on end # SiI device pci 6.0 on end
end
chip drivers/pci/onboard
device pci 6.0 on end
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

20
src/mainboard/tyan/s2881/devicetree.cb
View File

@@ -13,14 +13,10 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/amd8131 chip southbridge/amd/amd8131
# the on/off keyword is mandatory # the on/off keyword is mandatory
device pci 0.0 on device pci 0.0 on
chip drivers/pci/onboard device pci 9.0 on end # Broadcom 5704
device pci 9.0 on end # Broadcom 5704 device pci 9.1 on end
device pci 9.1 on end device pci a.0 on end # Adaptic
end device pci a.1 on end
chip drivers/pci/onboard
device pci a.0 on end # Adaptic
device pci a.1 on end
end
end end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on end device pci 1.0 on end
@@ -34,12 +30,8 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end device pci 0.1 on end
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
chip drivers/pci/onboard device pci 5.0 on end # SiI
device pci 5.0 on end # SiI device pci 6.0 on end
end
chip drivers/pci/onboard
device pci 6.0 on end
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

25
src/mainboard/tyan/s2882/Config.lb
View File

@@ -114,14 +114,10 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/amd8131 chip southbridge/amd/amd8131
# the on/off keyword is mandatory # the on/off keyword is mandatory
device pci 0.0 on device pci 0.0 on
chip drivers/pci/onboard device pci 6.0 on end # adaptec
device pci 6.0 on end # adaptec device pci 6.1 on end
device pci 6.1 on end device pci 9.0 on end # broadcom 5704
end device pci 9.1 on end
chip drivers/pci/onboard
device pci 9.0 on end # broadcom 5704
device pci 9.1 on end
end
end end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on end device pci 1.0 on end
@@ -135,16 +131,11 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end device pci 0.1 on end
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
chip drivers/pci/onboard device pci 5.0 on end
device pci 5.0 on end
end
# chip drivers/ati/ragexl # chip drivers/ati/ragexl
chip drivers/pci/onboard device pci 6.0 on end
device pci 6.0 on end # end
end device pci 8.0 on end #intel 10/100
chip drivers/pci/onboard
device pci 8.0 on end #intel 10/100
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

25
src/mainboard/tyan/s2882/devicetree.cb
View File

@@ -12,14 +12,10 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/amd8131 chip southbridge/amd/amd8131
# the on/off keyword is mandatory # the on/off keyword is mandatory
device pci 0.0 on device pci 0.0 on
chip drivers/pci/onboard device pci 6.0 on end # adaptec
device pci 6.0 on end # adaptec device pci 6.1 on end
device pci 6.1 on end device pci 9.0 on end # broadcom 5704
end device pci 9.1 on end
chip drivers/pci/onboard
device pci 9.0 on end # broadcom 5704
device pci 9.1 on end
end
end end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on end device pci 1.0 on end
@@ -33,16 +29,11 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end device pci 0.1 on end
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
chip drivers/pci/onboard device pci 5.0 on end
device pci 5.0 on end
end
# chip drivers/ati/ragexl # chip drivers/ati/ragexl
chip drivers/pci/onboard device pci 6.0 on end
device pci 6.0 on end # end
end device pci 8.0 on end #intel 10/100
chip drivers/pci/onboard
device pci 8.0 on end #intel 10/100
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

8
src/mainboard/tyan/s2885/Config.lb
View File

@@ -121,9 +121,7 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/amd8131 chip southbridge/amd/amd8131
# the on/off keyword is mandatory # the on/off keyword is mandatory
device pci 0.0 on device pci 0.0 on
chip drivers/pci/onboard device pci 9.0 on end # broadcom 5703
device pci 9.0 on end # broadcom 5703
end
end end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on end device pci 1.0 on end
@@ -137,9 +135,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end device pci 0.1 on end
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
chip drivers/pci/onboard device pci b.0 on end # SiI 3114
device pci b.0 on end # SiI 3114
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

8
src/mainboard/tyan/s2885/devicetree.cb
View File

@@ -19,9 +19,7 @@ chip northbridge/amd/amdk8/root_complex
chip southbridge/amd/amd8131 chip southbridge/amd/amd8131
# the on/off keyword is mandatory # the on/off keyword is mandatory
device pci 0.0 on device pci 0.0 on
chip drivers/pci/onboard device pci 9.0 on end # broadcom 5703
device pci 9.0 on end # broadcom 5703
end
end end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on end device pci 1.0 on end
@@ -35,9 +33,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end device pci 0.1 on end
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
chip drivers/pci/onboard device pci b.0 on end # SiI 3114
device pci b.0 on end # SiI 3114
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

10
src/mainboard/tyan/s2891/devicetree.cb
View File

@@ -104,9 +104,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 8.0 on end # SATA 0 device pci 8.0 on end # SATA 0
device pci 9.0 on # PCI device pci 9.0 on # PCI
# chip drivers/ati/ragexl # chip drivers/ati/ragexl
chip drivers/pci/onboard device pci 7.0 on end
device pci 7.0 on end
end
end end
device pci a.0 off end # NIC device pci a.0 off end # NIC
device pci b.0 off end # PCI E 3 device pci b.0 off end # PCI E 3
@@ -127,10 +125,8 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.0 on end device pci 0.0 on end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on device pci 1.0 on
chip drivers/pci/onboard device pci 9.0 on end
device pci 9.0 on end device pci 9.1 on end
device pci 9.1 on end
end
end end
device pci 1.1 on end device pci 1.1 on end
end end

15
src/mainboard/tyan/s2892/devicetree.cb
View File

@@ -105,12 +105,9 @@ chip northbridge/amd/amdk8/root_complex
device pci 8.0 on end # SATA 0 device pci 8.0 on end # SATA 0
device pci 9.0 on # PCI device pci 9.0 on # PCI
# chip drivers/ati/ragexl # chip drivers/ati/ragexl
chip drivers/pci/onboard device pci 6.0 on end
device pci 6.0 on end # end
end device pci 8.0 on end
chip drivers/pci/onboard
device pci 8.0 on end
end
end end
device pci a.0 off end # NIC device pci a.0 off end # NIC
device pci b.0 off end # PCI E 3 device pci b.0 off end # PCI E 3
@@ -131,10 +128,8 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.0 on end device pci 0.0 on end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on device pci 1.0 on
chip drivers/pci/onboard device pci 9.0 on end # broadcom 5704
device pci 9.0 on end # broadcom 5704 device pci 9.1 on end
device pci 9.1 on end
end
end end
device pci 1.1 on end device pci 1.1 on end
end end

6
src/mainboard/tyan/s2895/devicetree.cb
View File

@@ -111,10 +111,8 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.0 on end device pci 0.0 on end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on device pci 1.0 on
chip drivers/pci/onboard device pci 6.0 on end # lsi scsi
device pci 6.0 on end # lsi scsi device pci 6.1 on end
device pci 6.1 on end
end
end end
device pci 1.1 on end device pci 1.1 on end
end end

4
src/mainboard/tyan/s2912_fam10/Config.lb
View File

@@ -279,9 +279,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on device pci 6.0 on
chip drivers/pci/onboard device pci 4.0 on end
device pci 4.0 on end
end
end # PCI end # PCI
device pci 6.1 off end # AZA device pci 6.1 off end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC

4
src/mainboard/tyan/s2912_fam10/devicetree.cb
View File

@@ -112,9 +112,7 @@ chip northbridge/amd/amdfam10/root_complex
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on device pci 6.0 on
chip drivers/pci/onboard device pci 4.0 on end
device pci 4.0 on end
end
end # PCI end # PCI
device pci 6.1 off end # AZA device pci 6.1 off end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC

10
src/mainboard/tyan/s4880/Config.lb
View File

@@ -116,10 +116,8 @@ chip northbridge/amd/amdk8/root_complex
# device pci 4.1 on end # device pci 4.1 on end
# register "fw_address" = "0xfff8c000" # register "fw_address" = "0xfff8c000"
# end # end
chip drivers/pci/onboard device pci 9.0 on end
device pci 9.0 on end device pci 9.1 on end
device pci 9.1 on end
end
end end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on end device pci 1.0 on end
@@ -133,9 +131,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end device pci 0.1 on end
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
chip drivers/pci/onboard device pci 6.0 on end
device pci 6.0 on end
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

10
src/mainboard/tyan/s4880/devicetree.cb
View File

@@ -19,10 +19,8 @@ chip northbridge/amd/amdk8/root_complex
# device pci 4.1 on end # device pci 4.1 on end
# register "fw_address" = "0xfff8c000" # register "fw_address" = "0xfff8c000"
# end # end
chip drivers/pci/onboard device pci 9.0 on end
device pci 9.0 on end device pci 9.1 on end
device pci 9.1 on end
end
end end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on end device pci 1.0 on end
@@ -36,9 +34,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end device pci 0.1 on end
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
chip drivers/pci/onboard device pci 6.0 on end
device pci 6.0 on end
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

15
src/mainboard/tyan/s4882/Config.lb
View File

@@ -114,10 +114,8 @@ chip northbridge/amd/amdk8/root_complex
# device pci 4.1 on end # device pci 4.1 on end
# register "fw_address" = "0xfff8c000" # register "fw_address" = "0xfff8c000"
# end # end
chip drivers/pci/onboard device pci 9.0 on end #Broadcom
device pci 9.0 on end #Broadcom device pci 9.1 on end
device pci 9.1 on end
end
end end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on end device pci 1.0 on end
@@ -132,12 +130,9 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
#chip drivers/ati/ragexl #chip drivers/ati/ragexl
chip drivers/pci/onboard device pci 6.0 on end
device pci 6.0 on end #end
end device pci 5.0 on end #SiI
chip drivers/pci/onboard
device pci 5.0 on end #SiI
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

15
src/mainboard/tyan/s4882/devicetree.cb
View File

@@ -17,10 +17,8 @@ chip northbridge/amd/amdk8/root_complex
# device pci 4.1 on end # device pci 4.1 on end
# register "fw_address" = "0xfff8c000" # register "fw_address" = "0xfff8c000"
# end # end
chip drivers/pci/onboard device pci 9.0 on end #Broadcom
device pci 9.0 on end #Broadcom device pci 9.1 on end
device pci 9.1 on end
end
end end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on end device pci 1.0 on end
@@ -35,12 +33,9 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.2 off end device pci 0.2 off end
device pci 1.0 off end device pci 1.0 off end
#chip drivers/ati/ragexl #chip drivers/ati/ragexl
chip drivers/pci/onboard device pci 6.0 on end
device pci 6.0 on end #end
end device pci 5.0 on end #SiI
chip drivers/pci/onboard
device pci 5.0 on end #SiI
end
end end
device pci 1.0 on device pci 1.0 on
chip superio/winbond/w83627hf chip superio/winbond/w83627hf

5
src/mainboard/via/epia/Config.lb
View File

@@ -96,10 +96,7 @@ chip northbridge/via/vt8601
device pci_domain 0 on device pci_domain 0 on
device pci 0.0 on end # Northbridge device pci 0.0 on end # Northbridge
# device pci 0.1 on # AGP bridge # device pci 0.1 on # AGP bridge
# chip drivers/pci/onboard # Integrated VGA # device pci 0.0 on end # Integrated VGA
# device pci 0.0 on end
# register "rom_adress" = "0xfff80000"
# end
# end # end
chip southbridge/via/vt8231 chip southbridge/via/vt8231
register "enable_native_ide" = "0" register "enable_native_ide" = "0"

5
src/mainboard/via/epia/devicetree.cb
View File

@@ -2,10 +2,7 @@ chip northbridge/via/vt8601
device pci_domain 0 on device pci_domain 0 on
device pci 0.0 on end # Northbridge device pci 0.0 on end # Northbridge
# device pci 0.1 on # AGP bridge # device pci 0.1 on # AGP bridge
# chip drivers/pci/onboard # Integrated VGA # device pci 0.0 on end # Integrated VGA
# device pci 0.0 on end
# register "rom_adress" = "0xfff80000"
# end
# end # end
chip southbridge/via/vt8231 chip southbridge/via/vt8231
register "enable_native_ide" = "0" register "enable_native_ide" = "0"

4
src/mainboard/via/vt8454c/Config.lb
View File

@@ -121,9 +121,7 @@ chip northbridge/via/cx700
device pci 0.4 on end # Power Management device pci 0.4 on end # Power Management
device pci 0.7 on end # V-Link Controller device pci 0.7 on end # V-Link Controller
device pci 1.0 on # PCI Bridge device pci 1.0 on # PCI Bridge
chip drivers/pci/onboard device pci 0.0 on end # Onboard Video
device pci 0.0 on end
end # Onboard Video
end # PCI Bridge end # PCI Bridge
device pci f.0 on end # IDE/SATA device pci f.0 on end # IDE/SATA
#device pci f.1 on end # IDE #device pci f.1 on end # IDE

4
src/mainboard/via/vt8454c/devicetree.cb
View File

@@ -12,9 +12,7 @@ chip northbridge/via/cx700
device pci 0.4 on end # Power Management device pci 0.4 on end # Power Management
device pci 0.7 on end # V-Link Controller device pci 0.7 on end # V-Link Controller
device pci 1.0 on # PCI Bridge device pci 1.0 on # PCI Bridge
chip drivers/pci/onboard device pci 0.0 on end # Onboard Video
device pci 0.0 on end
end # Onboard Video
end # PCI Bridge end # PCI Bridge
device pci f.0 on end # IDE/SATA device pci f.0 on end # IDE/SATA
#device pci f.1 on end # IDE #device pci f.1 on end # IDE

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