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sb/intel/bd82x6x/lpc: Set up default LPC decode ranges

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This sets up some common default LPC decode ranges in a common place.
This may set up more decode ranges than needed but that typically does
not hurt. Mainboards needing additional ranges can do so in the
mainboard pch_enable_lpc hook.

Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans
2019-06-16 23:36:28 +02:00
committed by Patrick Georgi
parent a06689c7e7
commit d28d507190
37 changed files with 18 additions and 193 deletions
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1
src/mainboard/asus/h61m-cs/romstage.c
View File

@@ -29,7 +29,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN);
}
void mainboard_rcba_config(void)

1
src/mainboard/asus/maximus_iv_gene-z/romstage.c
View File

@@ -42,7 +42,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
void pch_enable_lpc(void)
{
pci_or_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN);
}
void mainboard_rcba_config(void)

6
src/mainboard/asus/p8z77-m_pro/romstage.c
View File

@@ -32,12 +32,6 @@
void pch_enable_lpc(void)
{
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF1_LPC_EN | CNF2_LPC_EN |
KBC_LPC_EN | COMB_LPC_EN);
/* Set COMB/COM2 IO range to 2F8h-2FFh */
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
}
void mainboard_rcba_config(void)