From d2a57693dfcdd1b35cb03ffdcc4acfd3f64f8cc1 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Tue, 2 Aug 2022 13:19:41 -0600 Subject: [PATCH] mb/system76/adl-p: galp6: Fix PCIe port registers Correct the PCH PCIe RP indexes, which were copied from darp8. Fixes using Ethernet and the SD card reader. Change-Id: If14dea0492f6b7bea62d482ab970fe43e17c107b Signed-off-by: Tim Crawford --- src/mainboard/system76/adl-p/variants/galp6/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb index 4aa5bd5195..84b0116742 100644 --- a/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb +++ b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb @@ -151,7 +151,7 @@ chip soc/intel/alderlake end device ref pcie_rp9 on # PCIe RP#9 x1, Clock 5 (CARD) - register "pch_pcie_rp[PCH_RP(6)]" = "{ + register "pch_pcie_rp[PCH_RP(9)]" = "{ .clk_src = 5, .clk_req = 5, .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, @@ -159,7 +159,7 @@ chip soc/intel/alderlake end device ref pcie_rp10 on # PCIe RP#10 x1, Clock 6 (GLAN) - register "pch_pcie_rp[PCH_RP(8)]" = "{ + register "pch_pcie_rp[PCH_RP(10)]" = "{ .clk_src = 6, .clk_req = 6, .flags = PCIE_RP_LTR | PCIE_RP_AER,