src: Remove unneeded include "{arch,cpu}/cpu.h"

Change-Id: I17c4fc4e3e2eeef7c720c6a020b37d8f7a0f57a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

src/arch/x86/acpi_s3.c

@@ -16,8 +16,8 @@
 #include <console/console.h>
 #include <string.h>
 #include <arch/acpi.h>
+#include <arch/cpu.h>
 #include <cbmem.h>
-#include <cpu/cpu.h>
 #include <fallback.h>
 #include <timestamp.h>
 #include <program_loading.h>

src/arch/x86/mpspec.c

@@ -16,7 +16,6 @@
 #include <console/console.h>
 #include <device/path.h>
 #include <device/pci_ids.h>
-#include <cpu/cpu.h>
 #include <arch/smp/mpspec.h>
 #include <string.h>
 #include <arch/cpu.h>

src/arch/x86/tables.c

@@ -16,7 +16,6 @@
  */
 
 #include <console/console.h>
-#include <cpu/cpu.h>
 #include <bootmem.h>
 #include <bootstate.h>
 #include <boot/tables.h>

src/cpu/allwinner/a10/cpu.c

@@ -19,11 +19,9 @@
 
 #include <console/console.h>
 #include <device/device.h>
-#include <cpu/cpu.h>
 #include <cbmem.h>
 #include <symbols.h>
 
-
 static void cpu_enable_resources(struct device *dev)
 {
 	ram_resource(dev, 0, (uintptr_t)_dram/KiB,

src/cpu/amd/car/disable_cache_as_ram.c

@@ -19,6 +19,7 @@
  * WARNING: this file will be used by both any AP cores and core 0 / node 0
  */
 
+#include <arch/cpu.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/msr.h>

src/cpu/amd/family_10h-family_15h/init_cpus.h

@@ -18,7 +18,6 @@
 
 #include <stdlib.h>
 #include <console/console.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/msr.h>

src/cpu/amd/family_10h-family_15h/processor_name.c

@@ -27,7 +27,6 @@
 #include <string.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
-#include <cpu/cpu.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <device/device.h>
 #include <device/pci.h>

src/cpu/amd/family_10h-family_15h/ram_calc.c

@@ -14,7 +14,7 @@
  * GNU General Public License for more details.
  */
 
-#include <cpu/cpu.h>
+#include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 

src/cpu/amd/quadcore/amd_sibling.c

@@ -13,9 +13,7 @@
  * GNU General Public License for more details.
  */
 
-
 #include <console/console.h>
-#include <cpu/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <device/device.h>
 #include <device/pci.h>

src/cpu/amd/quadcore/quadcore.c

@@ -15,6 +15,7 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/cpu.h>
 #include <console/console.h>
 #include <pc80/mc146818rtc.h>
 #if IS_ENABLED(CONFIG_HAVE_OPTION_TABLE)

src/cpu/amd/smm/smm_init.c

@@ -16,7 +16,6 @@
 
 #include <console/console.h>
 #include <arch/io.h>
-#include <cpu/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>

src/cpu/intel/car/romstage.c

@@ -11,7 +11,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/cpu.h>
 #include <console/console.h>
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>

src/cpu/intel/fsp_model_206ax/finalize.c

@@ -16,7 +16,7 @@
 
 #include <stdint.h>
 #include <stdlib.h>
-#include <cpu/cpu.h>
+#include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include "model_206ax.h"
 

src/cpu/intel/fsp_model_406dx/bootblock.c

@@ -15,7 +15,6 @@
  */
 
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/cache.h>
 #include <cpu/intel/microcode/microcode.c>
 #include <cpu/x86/msr.h>

src/cpu/intel/haswell/bootblock.c

@@ -14,7 +14,6 @@
  */
 
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>

src/cpu/intel/haswell/finalize.c

@@ -16,7 +16,7 @@
 
 #include <stdint.h>
 #include <stdlib.h>
-#include <cpu/cpu.h>
+#include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include "haswell.h"
 

src/cpu/intel/haswell/romstage.c

@@ -19,7 +19,6 @@
 #include <console/console.h>
 #include <arch/cpu.h>
 #include <cf9_reset.h>
-#include <cpu/cpu.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>

src/cpu/intel/haswell/smmrelocate.c

@@ -18,7 +18,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ops.h>
-#include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>

src/cpu/intel/hyperthreading/intel_sibling.c

@@ -12,7 +12,6 @@
  */
 
 #include <console/console.h>
-#include <cpu/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/intel/hyperthreading.h>
 #include <device/device.h>

src/cpu/intel/microcode/microcode.c

@@ -24,7 +24,7 @@
 #else
 #include <arch/cbfs.h>
 #endif
-#include <cpu/cpu.h>
+#include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/microcode.h>
 #include <rules.h>

src/cpu/intel/model_2065x/finalize.c

@@ -16,7 +16,7 @@
 
 #include <stdint.h>
 #include <stdlib.h>
-#include <cpu/cpu.h>
+#include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/speedstep.h>
 #include "model_2065x.h"

src/cpu/intel/model_206ax/finalize.c

@@ -16,7 +16,7 @@
 
 #include <stdint.h>
 #include <stdlib.h>
-#include <cpu/cpu.h>
+#include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/speedstep.h>
 #include "model_206ax.h"

src/cpu/intel/slot_1/l2_cache.c

@@ -40,7 +40,6 @@
 
 #include <stdint.h>
 #include <console/console.h>
-#include <cpu/cpu.h>
 #include <cpu/intel/l2_cache.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>

src/cpu/intel/smm/gen1/smmrelocate.c

@@ -21,7 +21,6 @@
 #include <string.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>

src/cpu/via/nano/update_ucode.c

@@ -18,7 +18,6 @@
 #include <cpu/x86/msr.h>
 #include <console/console.h>
 #include <stddef.h>
-#include <cpu/cpu.h>
 #include <arch/cpu.h>
 #include <cbfs.h>
 

src/cpu/x86/mtrr/mtrr.c

@@ -33,7 +33,6 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
 #include <arch/acpi.h>
 #include <memrange.h>
 #include <cpu/amd/mtrr.h>

src/cpu/x86/name/name.c

@@ -14,8 +14,8 @@
  */
 
 #include <string.h>
+#include <arch/cpu.h>
 #include <device/device.h>
-#include <cpu/cpu.h>
 #include <cpu/x86/name.h>
 
 void fill_processor_name(char *processor_name)

src/cpu/x86/pae/pgtbl.c

@@ -16,7 +16,6 @@
 #include <cbfs.h>
 #include <commonlib/helpers.h>
 #include <console/console.h>
-#include <cpu/cpu.h>
 #include <arch/cpu.h>
 #include <cpu/x86/cr.h>
 #include <cpu/x86/msr.h>

src/drivers/amd/agesa/state_machine.c

@@ -18,6 +18,7 @@
 #include <string.h>
 
 #include <arch/acpi.h>
+#include <arch/cpu.h>
 #include <bootstate.h>
 #include <cbfs.h>
 #include <cbmem.h>

src/drivers/gic/gic.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/cpu.h>
 #include <arch/io.h>
 #include <console/console.h>
 #include <gic.h>

src/drivers/i2c/w83793/w83793.c

@@ -15,7 +15,6 @@
  */
 
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <console/console.h>
 #include <device/device.h>
 #include "w83793.h"

src/drivers/intel/fsp1_1/stack.c

@@ -14,6 +14,7 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/cpu.h>
 #include <cbmem.h>
 #include <console/console.h>
 #include <cpu/x86/mtrr.h>

src/drivers/intel/fsp2_0/memory_init.c

@@ -13,7 +13,6 @@
 
 #include <security/vboot/antirollback.h>
 #include <arch/io.h>
-#include <arch/cpu.h>
 #include <arch/symbols.h>
 #include <assert.h>
 #include <cbfs.h>

src/drivers/intel/fsp2_0/notify.c

@@ -10,7 +10,6 @@
  * (at your option) any later version.
  */
 
-#include <arch/cpu.h>
 #include <bootstate.h>
 #include <console/console.h>
 #include <fsp/util.h>

src/drivers/intel/fsp2_0/silicon_init.c

@@ -10,7 +10,6 @@
  * (at your option) any later version.
  */
 
-#include <arch/cpu.h>
 #include <cbfs.h>
 #include <cbmem.h>
 #include <commonlib/fsp.h>

src/drivers/intel/fsp2_0/upd_display.c

@@ -9,7 +9,6 @@
  * (at your option) any later version.
  */
 
-#include <arch/cpu.h>
 #include <console/console.h>
 #include <fsp/util.h>
 #include <lib.h>

src/include/cpu/amd/model_10xxx_rev.h

@@ -16,8 +16,6 @@
 #ifndef __CPU_AMD_MODEL_10XXX_REV_H__
 #define __CPU_AMD_MODEL_10XXX_REV_H__
 
-#include <arch/cpu.h>
-
 int init_processor_name(void);
 
 /* place holder for Family 10 revision code */

src/include/cpu/x86/cr.h

@@ -19,7 +19,6 @@
 #if !defined(__ASSEMBLER__)
 
 #include <stdint.h>
-#include <arch/cpu.h>
 
 /* ROMCC apparently chokes certain clobber registers. */
 #if defined(__ROMCC__)

src/mainboard/adi/rcc-dff/romstage.c

@@ -23,7 +23,6 @@
 #include <southbridge/intel/fsp_rangeley/soc.h>
 #include <southbridge/intel/fsp_rangeley/gpio.h>
 #include <southbridge/intel/fsp_rangeley/romstage.h>
-#include <arch/cpu.h>
 #include "gpio.h"
 
 static void interrupt_routing_config(void)

src/mainboard/advansus/a785e-i/romstage.c

@@ -30,6 +30,7 @@
 #include <timestamp.h>
 #include <cpu/amd/model_10xxx_rev.h>
 #include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
 #include <commonlib/loglevel.h>
 #include <cpu/x86/bist.h>
 #include <superio/winbond/common/winbond.h>

src/mainboard/amd/bettong/mptable.c

@@ -19,7 +19,6 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 #include <southbridge/amd/common/amd_pci_util.h>

src/mainboard/amd/bettong/romstage.c

@@ -17,6 +17,7 @@
 #include <arch/acpi.h>
 #include <arch/io.h>
 #include <arch/stages.h>
+#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/bist.h>
 #include <cpu/amd/car.h>

src/mainboard/amd/bimini_fam10/romstage.c

@@ -24,6 +24,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/amd/db-ft3b-lc/mptable.c

@@ -20,7 +20,6 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/common/amd_pci_util.h>
 

src/mainboard/amd/gardenia/mptable.c

@@ -19,7 +19,6 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <soc/southbridge.h>
 #include <amdblocks/amd_pci_util.h>

src/mainboard/amd/lamar/mptable.c

@@ -19,7 +19,6 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/common/amd_pci_util.h>
 #include <drivers/generic/ioapic/chip.h>

src/mainboard/amd/mahogany_fam10/romstage.c

@@ -26,6 +26,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/amd/olivehill/mptable.c

@@ -19,7 +19,6 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 

src/mainboard/amd/olivehillplus/mptable.c

@@ -19,7 +19,6 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 

src/mainboard/amd/parmer/mptable.c

@@ -19,7 +19,6 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 

src/mainboard/amd/parmer/romstage.c

@@ -14,7 +14,6 @@
  */
 
 #include <arch/io.h>
-#include <arch/cpu.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 

src/mainboard/amd/serengeti_cheetah_fam10/romstage.c

@@ -24,6 +24,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/amd/thatcher/mptable.c

@@ -19,7 +19,6 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 

src/mainboard/amd/thatcher/romstage.c

@@ -21,7 +21,6 @@
 #include <arch/io.h>
 #include <arch/stages.h>
 #include <device/pnp_def.h>
-#include <arch/cpu.h>
 #include <commonlib/loglevel.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>

src/mainboard/amd/tilapia_fam10/romstage.c

@@ -24,6 +24,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/aopen/dxplplusu/romstage.c

@@ -16,7 +16,6 @@
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
-#include <arch/cpu.h>
 #include <stdlib.h>
 #include <cbmem.h>
 #include <console/console.h>

src/mainboard/asrock/imb-a180/mptable.c

@@ -19,7 +19,6 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 

src/mainboard/asus/am1i-a/mptable.c

@@ -20,7 +20,6 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/common/amd_pci_util.h>
 #include <drivers/generic/ioapic/chip.h>

src/mainboard/asus/f2a85-m/mptable.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/cpu.h>
 #include <arch/io.h>
 #include <arch/ioapic.h>
 #include <arch/smp/mpspec.h>
@@ -23,7 +22,6 @@
 #include <string.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 
-
 u8 picr_data[] = {
 	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
 	0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

src/mainboard/asus/kcma-d8/resourcemap.c

@@ -17,6 +17,8 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/cpu.h>
+
 static void setup_mb_resource_map(void)
 {
 	static const unsigned int fam15h_register_values[] = {

src/mainboard/asus/kcma-d8/romstage.c

@@ -22,6 +22,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/asus/kfsn4-dre/romstage.c

@@ -25,6 +25,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/asus/kgpe-d16/resourcemap.c

@@ -17,6 +17,8 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/cpu.h>
+
 static void setup_mb_resource_map(void)
 {
 	static const unsigned int fam15h_register_values[] = {

src/mainboard/asus/kgpe-d16/romstage.c

@@ -22,6 +22,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/asus/m4a78-em/romstage.c

@@ -25,6 +25,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/asus/m4a785-m/romstage.c

@@ -26,6 +26,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/asus/m5a88-v/romstage.c

@@ -26,6 +26,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/avalue/eax-785e/romstage.c

@@ -24,6 +24,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/bap/ode_e20XX/mptable.c

@@ -19,7 +19,6 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/common/amd_pci_util.h>
 #include <drivers/generic/ioapic/chip.h>

src/mainboard/bap/ode_e21XX/mptable.c

@@ -19,7 +19,6 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 

src/mainboard/biostar/a68n_5200/mptable.c

@@ -19,7 +19,6 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 

src/mainboard/biostar/am1ml/mptable.c

@@ -19,7 +19,6 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/common/amd_pci_util.h>
 #include <drivers/generic/ioapic/chip.h>

src/mainboard/gigabyte/ma785gm/romstage.c

@@ -22,6 +22,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/gigabyte/ma785gmt/romstage.c

@@ -22,6 +22,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/gigabyte/ma78gm/romstage.c

@@ -25,6 +25,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/gizmosphere/gizmo2/mptable.c

@@ -19,7 +19,6 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/common/amd_pci_util.h>
 #include <drivers/generic/ioapic/chip.h>

src/mainboard/google/butterfly/romstage.c

@@ -28,7 +28,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-#include <arch/cpu.h>
 #include <halt.h>
 #if IS_ENABLED(CONFIG_CHROMEOS)
 #include <vendorcode/google/chromeos/chromeos.h>

src/mainboard/google/kahlee/mptable.c

@@ -19,7 +19,6 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <soc/southbridge.h>
 #include <amdblocks/amd_pci_util.h>

src/mainboard/google/link/romstage.c

@@ -30,7 +30,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/common/gpio.h>
 #include "ec/google/chromeec/ec.h"
-#include <arch/cpu.h>
 #include <halt.h>
 #include <cbfs.h>
 

src/mainboard/google/nyan/romstage.c

@@ -14,7 +14,6 @@
  */
 
 #include <arch/cache.h>
-#include <arch/cpu.h>
 #include <arch/exception.h>
 #include <arch/io.h>
 #include <cbfs.h>

src/mainboard/google/nyan_big/romstage.c

@@ -14,7 +14,6 @@
  */
 
 #include <arch/cache.h>
-#include <arch/cpu.h>
 #include <arch/exception.h>
 #include <arch/io.h>
 #include <cbfs.h>

src/mainboard/google/nyan_blaze/romstage.c

@@ -14,7 +14,6 @@
  */
 
 #include <arch/cache.h>
-#include <arch/cpu.h>
 #include <arch/exception.h>
 #include <arch/io.h>
 #include <cbfs.h>

src/mainboard/google/parrot/romstage.c

@@ -28,7 +28,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-#include <arch/cpu.h>
 #include <halt.h>
 #include <cbfs.h>
 #include "ec/compal/ene932/ec.h"

src/mainboard/google/stout/romstage.c

@@ -29,7 +29,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-#include <arch/cpu.h>
 #include <halt.h>
 #include <bootmode.h>
 #include <cbfs.h>

src/mainboard/hp/abm/mptable.c

@@ -19,11 +19,9 @@
 #include <arch/ioapic.h>
 #include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 
-
 u8 picr_data[0x54] = {
 	0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
 	0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

src/mainboard/hp/dl165_g6_fam10/romstage.c

@@ -29,6 +29,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include "option_table.h"

src/mainboard/hp/pavilion_m6_1035dx/mptable.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/cpu.h>
 #include <arch/io.h>
 #include <arch/ioapic.h>
 #include <arch/smp/mpspec.h>
@@ -23,7 +22,6 @@
 #include <string.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 
-
 u8 picr_data[0x54] = {
 	0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
 	0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

src/mainboard/iei/kino-780am2-fam10/romstage.c

@@ -25,6 +25,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/intel/bayleybay_fsp/romstage.c

@@ -15,7 +15,6 @@
  */
 
 #include <stddef.h>
-#include <arch/cpu.h>
 #include <lib.h>
 #include <arch/io.h>
 #include <arch/cbfs.h>

src/mainboard/intel/cougar_canyon2/romstage.c

@@ -15,7 +15,6 @@
  * GNU General Public License for more details.
  */
 
-
 #include <stdint.h>
 #include <string.h>
 #include <lib.h>
@@ -36,7 +35,6 @@
 #include <southbridge/intel/fsp_bd82x6x/pch.h>
 #include <southbridge/intel/fsp_bd82x6x/gpio.h>
 #include <southbridge/intel/fsp_bd82x6x/me.h>
-#include <arch/cpu.h>
 #include "gpio.h"
 
 #define SIO_PORT 0x164e

src/mainboard/intel/emeraldlake2/romstage.c

@@ -29,7 +29,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-#include <arch/cpu.h>
 #include <halt.h>
 
 #define SIO_PORT 0x164e

src/mainboard/intel/harcuvar/acpi_tables.c

@@ -24,7 +24,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <cpu/cpu.h>
 #include <cpu/x86/msr.h>
 
 #include <soc/acpi.h>

src/mainboard/intel/littleplains/romstage.c

@@ -23,7 +23,6 @@
 #include <southbridge/intel/fsp_rangeley/soc.h>
 #include <southbridge/intel/fsp_rangeley/gpio.h>
 #include <southbridge/intel/fsp_rangeley/romstage.h>
-#include <arch/cpu.h>
 #include "gpio.h"
 
 static void interrupt_routing_config(void)

src/mainboard/intel/mohonpeak/romstage.c

@@ -23,7 +23,6 @@
 #include <southbridge/intel/fsp_rangeley/soc.h>
 #include <southbridge/intel/fsp_rangeley/gpio.h>
 #include <southbridge/intel/fsp_rangeley/romstage.h>
-#include <arch/cpu.h>
 #include "gpio.h"
 
 static void interrupt_routing_config(void)

src/mainboard/intel/stargo2/romstage.c

@@ -19,7 +19,6 @@
 #include <string.h>
 #include <lib.h>
 #include <timestamp.h>
-#include <arch/cpu.h>
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>

src/mainboard/jetway/pa78vm5/romstage.c

@@ -26,6 +26,7 @@
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <arch/io.h>
+#include <arch/cpu.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>

src/mainboard/kontron/ktqm77/romstage.c

@@ -27,7 +27,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-#include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <halt.h>
 #include <superio/winbond/common/winbond.h>

src/mainboard/lenovo/g505s/mptable.c

@@ -13,7 +13,6 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/cpu.h>
 #include <arch/io.h>
 #include <arch/ioapic.h>
 #include <arch/smp/mpspec.h>
@@ -23,7 +22,6 @@
 #include <string.h>
 #include <southbridge/amd/agesa/hudson/hudson.h>
 
-
 u8 picr_data[0x54] = {
 	0x1F,0x1f,0x1f,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
 	0x09,0x1F,0x1F,0x0B,0x1F,0x0B,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,

src/mainboard/lenovo/t520/romstage.c

@@ -29,8 +29,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-#include <arch/cpu.h>
-#include <cbfs.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
 #include <device/device.h>
 #include <device/pci.h>

src/mainboard/lenovo/x1_carbon_gen1/romstage.c

@@ -31,7 +31,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
-#include <arch/cpu.h>
 #include <cbfs.h>
 
 void pch_enable_lpc(void)