mb/system76/adl: Add Gazelle 18 (3050) as a variant

There will be two versions of firmware for the Gazelle 18:

- One for units using NVIDIA RTX 3050
- One for units using NVIDIA RTX 40x0

Change-Id: I7c1a51fda012fe4e7a43bbe5ef98a3aec38373a0
Signed-off-by: Tim Crawford <tcrawford@system76.com>

src/mainboard/system76/adl/Kconfig

@@ -29,6 +29,14 @@ config BOARD_SYSTEM76_GALP6
 	def_bool n
 	select BOARD_SYSTEM76_ADL_COMMON
 
+config BOARD_SYSTEM76_GAZE18_3050
+	def_bool n
+	select BOARD_SYSTEM76_ADL_COMMON
+	select DRIVERS_GFX_NVIDIA
+	select EC_SYSTEM76_EC_COLOR_KEYBOARD
+	select EC_SYSTEM76_EC_DGPU
+	select SOC_INTEL_RAPTORLAKE
+
 config BOARD_SYSTEM76_LEMP11
 	def_bool n
 	select BOARD_SYSTEM76_ADL_COMMON
@@ -57,6 +65,7 @@ config MAINBOARD_DIR
 config VARIANT_DIR
 	default "darp8" if BOARD_SYSTEM76_DARP8
 	default "galp6" if BOARD_SYSTEM76_GALP6
+	default "gaze18-3050" if BOARD_SYSTEM76_GAZE18_3050
 	default "lemp11" if BOARD_SYSTEM76_LEMP11
 	default "oryp9" if BOARD_SYSTEM76_ORYP9
 	default "oryp10" if BOARD_SYSTEM76_ORYP10
@@ -67,6 +76,7 @@ config OVERRIDE_DEVICETREE
 config MAINBOARD_PART_NUMBER
 	default "darp8" if BOARD_SYSTEM76_DARP8
 	default "galp6" if BOARD_SYSTEM76_GALP6
+	default "gaze18-3050" if BOARD_SYSTEM76_GAZE18_3050
 	default "lemp11" if BOARD_SYSTEM76_LEMP11
 	default "oryp9" if BOARD_SYSTEM76_ORYP9
 	default "oryp10" if BOARD_SYSTEM76_ORYP10
@@ -74,18 +84,20 @@ config MAINBOARD_PART_NUMBER
 config MAINBOARD_SMBIOS_PRODUCT_NAME
 	default "Darter Pro" if BOARD_SYSTEM76_DARP8
 	default "Galago Pro" if BOARD_SYSTEM76_GALP6
+	default "Gazelle" if BOARD_SYSTEM76_GAZE18_3050
 	default "Lemur Pro" if BOARD_SYSTEM76_LEMP11
 	default "Oryx Pro" if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10
 
 config MAINBOARD_VERSION
 	default "darp8" if BOARD_SYSTEM76_DARP8
 	default "galp6" if BOARD_SYSTEM76_GALP6
+	default "gaze18-3050" if BOARD_SYSTEM76_GAZE18_3050
 	default "lemp11" if BOARD_SYSTEM76_LEMP11
 	default "oryp9" if BOARD_SYSTEM76_ORYP9
 	default "oryp10" if BOARD_SYSTEM76_ORYP10
 
 config CBFS_SIZE
-	default 0xA00000
+	default 0x1000000
 
 config CONSOLE_POST
 	default y

src/mainboard/system76/adl/Kconfig.name

@@ -4,6 +4,9 @@ config BOARD_SYSTEM76_DARP8
 config BOARD_SYSTEM76_GALP6
 	bool "galp6"
 
+config BOARD_SYSTEM76_GAZE18_3050
+	bool "gaze18-3050"
+
 config BOARD_SYSTEM76_LEMP11
 	bool "lemp11"
 

src/mainboard/system76/adl/variants/gaze18-3050/board_info.txt

@@ -0,0 +1,2 @@
+Board name: gaze18-3050
+Release year: 2023

src/mainboard/system76/adl/variants/gaze18-3050/gpio.c

@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config gpio_table[] = {
+	PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1),
+	PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1),
+	PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
+	PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD7, 0, DEEP),
+	PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
+	PAD_CFG_GPO(GPD9, 0, PWROK),
+	PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPD11, NONE, PWROK, NF1),
+	PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1),
+	PAD_CFG_GPO(GPP_A6, 0, DEEP),
+	PAD_CFG_GPO(GPP_A7, 0, DEEP),
+	PAD_CFG_GPO(GPP_A8, 1, PLTRST),
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_A11, 0, DEEP),
+	PAD_CFG_GPO(GPP_A12, 0, DEEP),
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST),
+	PAD_CFG_GPO(GPP_A14, 0, DEEP),
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_A17, 0x80100100, 0x0000),
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_A19, NONE, DEEP),
+	PAD_CFG_GPO(GPP_A20, 0, DEEP),
+	PAD_CFG_GPO(GPP_A21, 0, DEEP),
+	PAD_CFG_GPO(GPP_A22, 0, DEEP),
+	PAD_CFG_GPO(GPP_A23, 0, DEEP),
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_B2, 0, DEEP),
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP),
+	PAD_CFG_GPI(GPP_B4, NONE, DEEP),
+	PAD_CFG_GPO(GPP_B5, 0, DEEP),
+	PAD_CFG_GPO(GPP_B6, 0, DEEP),
+	PAD_CFG_GPO(GPP_B7, 0, DEEP),
+	PAD_CFG_GPO(GPP_B8, 0, DEEP),
+	PAD_CFG_GPO(GPP_B9, 0, DEEP),
+	PAD_CFG_GPO(GPP_B10, 0, DEEP),
+	PAD_NC(GPP_B11, NONE),
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	_PAD_CFG_STRUCT(GPP_B14, 0x44001100, 0x0000),
+	PAD_CFG_GPO(GPP_B15, 0, DEEP),
+	PAD_CFG_GPO(GPP_B16, 0, DEEP),
+	PAD_CFG_GPO(GPP_B17, 0, DEEP),
+	PAD_CFG_GPO(GPP_B18, 0, DEEP),
+	PAD_CFG_GPO(GPP_B19, 0, DEEP),
+	PAD_CFG_GPO(GPP_B20, 0, DEEP),
+	PAD_CFG_GPO(GPP_B21, 0, DEEP),
+	PAD_CFG_GPO(GPP_B22, 0, DEEP),
+	PAD_CFG_GPO(GPP_B23, 0, DEEP),
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_C2, 1, PLTRST),
+	PAD_CFG_GPI(GPP_C3, NONE, DEEP),
+	PAD_CFG_GPI(GPP_C4, NONE, DEEP),
+	PAD_CFG_GPO(GPP_C5, 0, DEEP),
+	PAD_NC(GPP_C6, NONE),
+	PAD_NC(GPP_C7, NONE),
+	PAD_NC(GPP_C8, NONE),
+	PAD_NC(GPP_C9, NONE),
+	PAD_NC(GPP_C10, NONE),
+	PAD_NC(GPP_C11, NONE),
+	PAD_NC(GPP_C12, NONE),
+	PAD_NC(GPP_C13, NONE),
+	PAD_NC(GPP_C14, NONE),
+	PAD_NC(GPP_C15, NONE),
+	PAD_NC(GPP_C16, NONE),
+	PAD_NC(GPP_C17, NONE),
+	PAD_NC(GPP_C18, NONE),
+	PAD_NC(GPP_C19, NONE),
+	PAD_NC(GPP_C20, NONE),
+	PAD_NC(GPP_C21, NONE),
+	PAD_NC(GPP_C22, NONE),
+	PAD_NC(GPP_C23, NONE),
+	PAD_CFG_GPO(GPP_D0, 1, DEEP),
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP),
+	PAD_NC(GPP_D2, NONE),
+	PAD_CFG_GPO(GPP_D3, 0, DEEP),
+	PAD_CFG_GPI(GPP_D4, NONE, DEEP),
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_D9, 0, DEEP),
+	PAD_CFG_GPO(GPP_D10, 0, DEEP),
+	PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF2),
+	PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF2),
+	PAD_CFG_GPI(GPP_D13, NONE, DEEP),
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D15, 0, DEEP),
+	PAD_CFG_GPO(GPP_D16, 1, PLTRST),
+	PAD_CFG_GPO(GPP_D17, 0, DEEP),
+	PAD_CFG_GPO(GPP_D18, 0, DEEP),
+	PAD_CFG_GPO(GPP_D19, 0, DEEP),
+	PAD_CFG_GPI(GPP_E0, NONE, DEEP),
+	_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000),
+	PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+	PAD_CFG_GPO(GPP_E3, 1, PLTRST),
+	PAD_CFG_GPI(GPP_E4, NONE, DEEP),
+	PAD_CFG_GPI(GPP_E5, NONE, DEEP),
+	PAD_CFG_GPO(GPP_E6, 0, DEEP),
+	PAD_CFG_GPI(GPP_E7, NONE, DEEP),
+	PAD_CFG_GPO(GPP_E8, 0, DEEP),
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E10, 0, DEEP),
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+	PAD_CFG_GPO(GPP_E12, 0, DEEP),
+	PAD_CFG_GPO(GPP_E13, 0, DEEP),
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_E15, 0, DEEP),
+	PAD_CFG_GPO(GPP_E16, 0, DEEP),
+	PAD_CFG_GPI(GPP_E17, NONE, DEEP),
+	PAD_CFG_GPO(GPP_E18, 0, DEEP),
+	_PAD_CFG_STRUCT(GPP_E19, 0x44001600, 0x3c00),
+	PAD_CFG_GPO(GPP_E20, 0, DEEP),
+	PAD_CFG_GPO(GPP_E21, 0, DEEP),
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_F7, 1, DEEP),
+	PAD_CFG_GPO(GPP_F8, 0, DEEP),
+	PAD_CFG_GPO(GPP_F9, 0, DEEP),
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	PAD_NC(GPP_F11, NONE),
+	PAD_CFG_GPI(GPP_F12, NONE, PLTRST),
+	PAD_CFG_GPI(GPP_F13, NONE, PLTRST),
+	PAD_NC(GPP_F14, NONE),
+	PAD_NC(GPP_F15, NONE),
+	PAD_CFG_GPO(GPP_F16, 0, DEEP),
+	PAD_CFG_GPO(GPP_F17, 0, DEEP),
+	PAD_CFG_GPO(GPP_F18, 0, DEEP),
+	PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_F20, 1, PLTRST),
+	PAD_CFG_GPO(GPP_F21, 0, DEEP),
+	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_H0, 0, DEEP),
+	PAD_CFG_GPO(GPP_H1, 0, DEEP),
+	PAD_CFG_GPO(GPP_H2, 0, DEEP),
+	PAD_CFG_GPI(GPP_H3, NONE, DEEP),
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	PAD_CFG_GPI(GPP_H6, NONE, DEEP),
+	PAD_CFG_GPI(GPP_H7, NONE, DEEP),
+	PAD_CFG_GPO(GPP_H8, 0, DEEP),
+	PAD_CFG_GPO(GPP_H9, 0, DEEP),
+	PAD_CFG_GPI(GPP_H10, NONE, DEEP),
+	PAD_CFG_GPI(GPP_H11, NONE, DEEP),
+	PAD_CFG_GPO(GPP_H12, 0, DEEP),
+	_PAD_CFG_STRUCT(GPP_H13, 0x04001500, 0x0000),
+	PAD_CFG_GPO(GPP_H14, 0, DEEP),
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_H16, 0, DEEP),
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_H19, 0, DEEP),
+	PAD_NC(GPP_H20, NONE),
+	PAD_NC(GPP_H21, NONE),
+	PAD_NC(GPP_H22, NONE),
+	PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2),
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1),
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1),
+	PAD_CFG_GPO(GPP_R5, 0, DEEP),
+	PAD_CFG_GPO(GPP_R6, 0, DEEP),
+	PAD_CFG_GPO(GPP_R7, 0, DEEP),
+	PAD_CFG_GPO(GPP_S0, 0, DEEP),
+	PAD_CFG_GPO(GPP_S1, 0, DEEP),
+	PAD_CFG_GPO(GPP_S2, 0, DEEP),
+	PAD_CFG_GPO(GPP_S3, 0, DEEP),
+	PAD_CFG_GPO(GPP_S4, 0, DEEP),
+	PAD_CFG_GPO(GPP_S5, 0, DEEP),
+	PAD_CFG_GPO(GPP_S6, 0, DEEP),
+	PAD_CFG_GPO(GPP_S7, 0, DEEP),
+	PAD_CFG_GPO(GPP_T2, 0, DEEP),
+	PAD_CFG_GPO(GPP_T3, 0, DEEP),
+};
+
+void mainboard_configure_gpios(void)
+{
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}

src/mainboard/system76/adl/variants/gaze18-3050/gpio_early.c

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <mainboard/gpio.h>
+#include <soc/gpio.h>
+
+static const struct pad_config early_gpio_table[] = {
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
+};
+
+void mainboard_configure_early_gpios(void)
+{
+	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}

src/mainboard/system76/adl/variants/gaze18-3050/hda_verb.c

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* Realtek, ALC256 */
+	0x10ec0256, /* Vendor ID */
+	0x15585630, /* Subsystem ID */
+	12, /* Number of entries */
+	AZALIA_SUBVENDOR(0, 0x15585630),
+	AZALIA_RESET(1),
+	AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
+	AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02a11040),
+	AZALIA_PIN_CFG(0, 0x1d, 0x41700001),
+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x21, 0x02211020),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;

src/mainboard/system76/adl/variants/gaze18-3050/include/variant/gpio.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N
+#define DGPU_PWR_EN
+#define DGPU_GC6
+#define DGPU_SSID
+
+#endif

src/mainboard/system76/adl/variants/gaze18-3050/overridetree.cb

@@ -0,0 +1,11 @@
+chip soc/intel/alderlake
+	device domain 0 on
+		subsystemid 0x1558 0x5630 inherit
+
+		device ref pcie5_0 off
+		end
+
+		device ref pcie4_0 off
+		end
+	end
+end

src/mainboard/system76/adl/variants/gaze18-3050/romstage.c

@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/gfx/nvidia/gpu.h>
+#include <soc/meminit.h>
+#include <soc/romstage.h>
+#include <variant/gpio.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg board_cfg = {
+		.type = MEM_TYPE_DDR5,
+		.rcomp = { .resistor = 100, },
+		.ect = true,
+		.LpDdrDqDqsReTraining = 1,
+	};
+	const struct mem_spd spd_info = {
+		.topo = MEM_TOPO_DIMM_MODULE,
+		.smbus = {
+			[0] = { .addr_dimm[0] = 0x50, },
+			[1] = { .addr_dimm[0] = 0x52, },
+		},
+	};
+	const bool half_populated = false;
+
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
+	// Set primary display to internal graphics
+	mupd->FspmConfig.PrimaryDisplay = 0;
+
+	mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
+	mupd->FspmConfig.DmiMaxLinkSpeed = 4;
+	mupd->FspmConfig.GpioOverride = 0;
+
+	memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
+}