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Add more RPP-S PCI ID definitions

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Change-Id: I3682701a169dd51b1e55227b4e089310bcf42a0f
This commit is contained in:
Jeremy Soller
2023-02-10 12:05:25 -07:00
parent 74e0453ef2
commit d30cad4127
5 changed files with 14 additions and 0 deletions
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7
src/include/device/pci_ids.h
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@@ -3565,6 +3565,7 @@
#define PCI_DID_INTEL_MTL_SATA 0x7e63 #define PCI_DID_INTEL_MTL_SATA 0x7e63
#define PCI_DID_INTEL_RPP_P_SATA_1 0x51d3 #define PCI_DID_INTEL_RPP_P_SATA_1 0x51d3
#define PCI_DID_INTEL_RPP_P_SATA_2 0x51d7 #define PCI_DID_INTEL_RPP_P_SATA_2 0x51d7
#define PCI_DID_INTEL_RPP_S_SATA 0x7a62
/* Intel PMC device Ids */ /* Intel PMC device Ids */
#define PCI_DID_INTEL_SPT_LP_PMC 0x9d21 #define PCI_DID_INTEL_SPT_LP_PMC 0x9d21
@@ -3787,6 +3788,7 @@
#define PCI_DID_INTEL_RPP_S_UART0 0x7a28 #define PCI_DID_INTEL_RPP_S_UART0 0x7a28
#define PCI_DID_INTEL_RPP_S_UART1 0x7a29 #define PCI_DID_INTEL_RPP_S_UART1 0x7a29
#define PCI_DID_INTEL_RPP_S_UART2 0x7a7e #define PCI_DID_INTEL_RPP_S_UART2 0x7a7e
#define PCI_DID_INTEL_RPP_S_UART3 0x7a5c
#define PCI_DID_INTEL_MTL_UART0 0x7e25 #define PCI_DID_INTEL_MTL_UART0 0x7e25
#define PCI_DID_INTEL_MTL_UART1 0x7e26 #define PCI_DID_INTEL_MTL_UART1 0x7e26
@@ -4387,6 +4389,7 @@
#define PCI_DID_INTEL_MTL_XDCI 0x7e7e #define PCI_DID_INTEL_MTL_XDCI 0x7e7e
#define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1 #define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1
#define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1
#define PCI_DID_INTEL_RPP_S_XDCI 0x7a61
/* Intel SD device Ids */ /* Intel SD device Ids */
#define PCI_DID_INTEL_LPT_LP_SD 0x9c35 #define PCI_DID_INTEL_LPT_LP_SD 0x9c35
@@ -4527,6 +4530,10 @@
#define PCI_DID_INTEL_MTL_CNVI_WIFI_1 0x7e41 #define PCI_DID_INTEL_MTL_CNVI_WIFI_1 0x7e41
#define PCI_DID_INTEL_MTL_CNVI_WIFI_2 0x7e42 #define PCI_DID_INTEL_MTL_CNVI_WIFI_2 0x7e42
#define PCI_DID_INTEL_MTL_CNVI_WIFI_3 0x7e43 #define PCI_DID_INTEL_MTL_CNVI_WIFI_3 0x7e43
#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_0 0x7a70
#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_1 0x7a71
#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_2 0x7a72
#define PCI_DID_INTEL_RPL_S_CNVI_WIFI_3 0x7a73
/* Intel Crashlog */ /* Intel Crashlog */
#define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d #define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d

4
src/soc/intel/common/block/cnvi/cnvi.c
View File

@@ -54,6 +54,10 @@ static const unsigned short wifi_pci_device_ids[] = {
PCI_DID_INTEL_ADL_N_CNVI_WIFI_1, PCI_DID_INTEL_ADL_N_CNVI_WIFI_1,
PCI_DID_INTEL_ADL_N_CNVI_WIFI_2, PCI_DID_INTEL_ADL_N_CNVI_WIFI_2,
PCI_DID_INTEL_ADL_N_CNVI_WIFI_3, PCI_DID_INTEL_ADL_N_CNVI_WIFI_3,
PCI_DID_INTEL_RPL_S_CNVI_WIFI_0,
PCI_DID_INTEL_RPL_S_CNVI_WIFI_1,
PCI_DID_INTEL_RPL_S_CNVI_WIFI_2,
PCI_DID_INTEL_RPL_S_CNVI_WIFI_3,
0 0
}; };

1
src/soc/intel/common/block/sata/sata.c
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@@ -16,6 +16,7 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_MTL_SATA, PCI_DID_INTEL_MTL_SATA,
PCI_DID_INTEL_RPP_P_SATA_1, PCI_DID_INTEL_RPP_P_SATA_1,
PCI_DID_INTEL_RPP_P_SATA_2, PCI_DID_INTEL_RPP_P_SATA_2,
PCI_DID_INTEL_RPP_S_SATA,
PCI_DID_INTEL_LWB_SATA_AHCI, PCI_DID_INTEL_LWB_SATA_AHCI,
PCI_DID_INTEL_LWB_SSATA_AHCI, PCI_DID_INTEL_LWB_SSATA_AHCI,
PCI_DID_INTEL_LWB_SATA_RAID, PCI_DID_INTEL_LWB_SATA_RAID,

1
src/soc/intel/common/block/uart/uart.c
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@@ -410,6 +410,7 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_RPP_S_UART0, PCI_DID_INTEL_RPP_S_UART0,
PCI_DID_INTEL_RPP_S_UART1, PCI_DID_INTEL_RPP_S_UART1,
PCI_DID_INTEL_RPP_S_UART2, PCI_DID_INTEL_RPP_S_UART2,
PCI_DID_INTEL_RPP_S_UART3,
0, 0,
}; };

1
src/soc/intel/common/block/xdci/xdci.c
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@@ -43,6 +43,7 @@ static const unsigned short pci_device_ids[] = {
PCI_DID_INTEL_ADP_P_XDCI, PCI_DID_INTEL_ADP_P_XDCI,
PCI_DID_INTEL_ADP_S_XDCI, PCI_DID_INTEL_ADP_S_XDCI,
PCI_DID_INTEL_ADP_M_XDCI, PCI_DID_INTEL_ADP_M_XDCI,
PCI_DID_INTEL_RPP_S_XDCI,
0 0
}; };