- A new test case for romcc
- Minor romcc fixes - In smbus_wail_until_done a romcc glitch with || in romcc where it likes to run out of registers. Use | to be explicit that I don't need the short circuiting behavior. - Remove unused #defines from coherent_ht.c - Update the test in auto.c to 512M - Add definition of log2 to romcc_io.h - Implement SPD memory sizing in raminit.c - Reduce the number of memory devices back 2 to for the SOLO board. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@883 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Eric Biederman
@@ -1,3 +1,4 @@
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#include <cpu/k8/mtrr.h>
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#define MEMORY_SUSE_SOLO 1 /* SuSE Solo configuration */
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#define MEMORY_LNXI_SOLO 2 /* LNXI Solo configuration */
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#define MEMORY_LNXI_HDAMA 3 /* LNXI HDAMA configuration */
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@@ -1112,6 +1113,192 @@ static void sdram_set_registers(void)
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print_debug("done.\r\n");
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}
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struct dimm_size {
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unsigned long side1;
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unsigned long side2;
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};
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static struct dimm_size spd_get_dimm_size(unsigned device)
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{
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/* Calculate the log base 2 size of a DIMM in bits */
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struct dimm_size sz;
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int value, low;
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sz.side1 = 0;
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sz.side2 = 0;
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/* Note it might be easier to use byte 31 here, it has the DIMM size as
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* a multiple of 4MB. The way we do it now we can size both
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* sides of an assymetric dimm.
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*/
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value = smbus_read_byte(device, 3); /* rows */
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if (value < 0) return sz;
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sz.side1 += value & 0xf;
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value = smbus_read_byte(device, 4); /* columns */
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if (value < 0) return sz;
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sz.side1 += value & 0xf;
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value = smbus_read_byte(device, 17); /* banks */
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if (value < 0) return sz;
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sz.side1 += log2(value & 0xff);
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/* Get the module data widht and convert it to a power of two */
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value = smbus_read_byte(device, 7); /* (high byte) */
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if (value < 0) return sz;
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value &= 0xff;
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value <<= 8;
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low = smbus_read_byte(device, 6); /* (low byte) */
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if (low < 0) return sz;
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value = value | (low & 0xff);
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sz.side1 += log2(value);
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/* side 2 */
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value = smbus_read_byte(device, 5); /* number of physical banks */
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if (value <= 1) return sz;
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/* Start with the symmetrical case */
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sz.side2 = sz.side1;
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value = smbus_read_byte(device, 3); /* rows */
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if (value < 0) return sz;
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if ((value & 0xf0) == 0) return sz; /* If symmetrical we are done */
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sz.side2 -= (value & 0x0f); /* Subtract out rows on side 1 */
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sz.side2 += ((value >> 4) & 0x0f); /* Add in rows on side 2 */
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value = smbus_read_byte(device, 4); /* columns */
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if (value < 0) return sz;
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sz.side2 -= (value & 0x0f); /* Subtract out columns on side 1 */
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sz.side2 += ((value >> 4) & 0x0f); /* Add in columsn on side 2 */
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return sz;
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}
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static unsigned spd_to_dimm_side0(unsigned device)
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{
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return (device - SMBUS_MEM_DEVICE_START) << 1;
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}
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static unsigned spd_to_dimm_side1(unsigned device)
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{
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return ((device - SMBUS_MEM_DEVICE_START) << 1) + 1;
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}
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static void set_dimm_size(unsigned long size, unsigned index)
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{
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unsigned value = 0;
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/* Make certain the dimm is at least 32MB */
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if (size >= (25 + 3)) {
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/* Place the dimm size in 32 MB quantities in the bits 31 - 21.
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* The initialize dimm size is in bits.
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* Set the base enable bit0.
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*/
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value = (1 << ((size - (25 + 3)) + 21)) | 1;
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}
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/* Set the appropriate DIMM base address register */
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pci_write_config32(PCI_DEV(0, 0x18, 2), 0x40 + (index << 2), value);
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}
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static void spd_set_ram_size(void)
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{
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unsigned device;
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for(device = SMBUS_MEM_DEVICE_START;
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device <= SMBUS_MEM_DEVICE_END;
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device += SMBUS_MEM_DEVICE_INC)
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{
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struct dimm_size sz;
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sz = spd_get_dimm_size(device);
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set_dimm_size(sz.side1, spd_to_dimm_side0(device));
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set_dimm_size(sz.side2, spd_to_dimm_side1(device));
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}
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}
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static void set_top_mem(unsigned tom_k)
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{
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/* Error if I don't have memory */
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if (!tom_k) {
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die("No memory");
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}
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/* Now set top of memory */
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msr_t msr;
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msr.lo = (tom_k & 0x003fffff) << 10;
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msr.hi = (tom_k & 0xffc00000) >> 22;
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wrmsr(TOP_MEM, msr);
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#if 1
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/* And report the amount of memory. (I run out of registers if i don't) */
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print_debug("RAM: 0x");
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print_debug_hex32(tom_k);
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print_debug(" KB\r\n");
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#endif
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}
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static void order_dimms(void)
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{
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unsigned long tom;
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unsigned mask;
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unsigned index;
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/* Remember which registers we have used in the high 8 bits of tom */
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tom = 0;
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for(;;) {
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/* Find the largest remaining canidate */
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unsigned canidate;
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uint32_t csbase, csmask;
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unsigned size;
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csbase = 0;
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canidate = 0;
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for(index = 0; index < 8; index++) {
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uint32_t value;
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value = pci_read_config32(PCI_DEV(0, 0x18, 2), 0x40 + (index << 2));
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/* Is it enabled? */
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if (!(value & 1)) {
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continue;
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}
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/* Is it greater? */
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if (value <= csbase) {
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continue;
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}
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/* Has it already been selected */
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if (tom & (1 << (index + 24))) {
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continue;
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}
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/* I have a new canidate */
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csbase = value;
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canidate = index;
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}
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/* See if I have found a new canidate */
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if (csbase == 0) {
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break;
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}
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/* Remember I have used this register */
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tom |= (1 << (canidate + 24));
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/* Remember the dimm size */
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size = csbase >> 21;
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/* Recompute the cs base register value */
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csbase = (tom << 21) | 1;
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/* Increment the top of memory */
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tom += size;
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/* Compute the memory mask */
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csmask = ((size -1) << 21);
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csmask |= 0xfe00; /* For now don't optimize */
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/* Write the new base register */
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pci_write_config32(PCI_DEV(0, 0x18, 2), 0x40 + (canidate << 2), csbase);
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pci_write_config32(PCI_DEV(0, 0x18, 2), 0x60 + (canidate << 2), csmask);
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}
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set_top_mem((tom & ~0xff000000) << 15);
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}
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#define DRAM_CONFIG_LOW 0x90
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#define DCL_DLL_Disable (1<<0)
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#define DCL_D_DRV (1<<1)
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@@ -1122,20 +1309,21 @@ static void sdram_set_registers(void)
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#define DCL_MemClrStatus (1<<11)
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#define DCL_DimmEcEn (1<<17)
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#define NODE_ID 0x60
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#define HT_INIT_CONTROL 0x6c
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#define HTIC_ColdR_Detect (1<<4)
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#define HTIC_BIOSR_Detect (1<<5)
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#define HTIC_INIT_Detect (1<<6)
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static void sdram_set_spd_registers(void)
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static void spd_set_ecc_mode(void)
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{
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unsigned long dcl;
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dcl = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW);
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/* Until I know what is going on disable ECC support */
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dcl &= ~DCL_DimmEcEn;
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pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, dcl);
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}
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static void sdram_set_spd_registers(void)
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{
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spd_set_ram_size();
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spd_set_ecc_mode();
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order_dimms();
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}
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#define TIMEOUT_LOOPS 300000
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