soc/intel/skylake: Add support in SKL for PMC common code
Change-Id: I3742f9c22d990edd918713155ae0bb1853663b6f Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/20499 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Shaunak Saha
committed by
Aaron Durbin
Aaron Durbin
parent
f073872e22
commit
d347680995
@ -26,6 +26,7 @@
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#include <device/pci.h>
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#include <device/pci_def.h>
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#include <console/console.h>
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#include <intelblocks/pmclib.h>
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#include <halt.h>
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#include <intelblocks/lpc_lib.h>
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#include <rules.h>
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@ -41,141 +42,13 @@
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#include <vboot/vbnv.h>
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#include "chip.h"
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/* Print status bits with descriptive names */
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static void print_status_bits(u32 status, const char * const bit_names[])
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{
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int i;
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if (!status)
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return;
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for (i = 31; i >= 0; i--) {
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if (status & (1 << i)) {
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if (bit_names[i])
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printk(BIOS_DEBUG, "%s ", bit_names[i]);
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else
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printk(BIOS_DEBUG, "BIT%d ", i);
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}
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}
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}
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/* Print status bits as GPIO numbers */
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static void print_gpio_status(u32 status, int start)
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{
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int i;
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if (!status)
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return;
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for (i = 31; i >= 0; i--) {
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if (status & (1 << i))
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printk(BIOS_DEBUG, "GPIO%d ", start + i);
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}
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}
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/*
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* PM1_CNT
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*/
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/* Enable events in PM1 control register */
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void enable_pm1_control(u32 mask)
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{
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u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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pm1_cnt |= mask;
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outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
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}
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/* Disable events in PM1 control register */
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void disable_pm1_control(u32 mask)
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{
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u32 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
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pm1_cnt &= ~mask;
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outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
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}
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/*
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* PM1
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*/
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/* Clear and return PM1 status register */
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static u16 reset_pm1_status(void)
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{
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u16 pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
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outw(pm1_sts, ACPI_BASE_ADDRESS + PM1_STS);
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return pm1_sts;
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}
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/* Print PM1 status bits */
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static u16 print_pm1_status(u16 pm1_sts)
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{
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static const char * const pm1_sts_bits[] = {
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[0] = "TMROF",
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[4] = "BM",
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[5] = "GBL",
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[8] = "PWRBTN",
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[10] = "RTC",
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[11] = "PRBTNOR",
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[14] = "PCIEXPWAK",
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[15] = "WAK",
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};
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if (!pm1_sts)
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return 0;
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printk(BIOS_SPEW, "PM1_STS: ");
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print_status_bits(pm1_sts, pm1_sts_bits);
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printk(BIOS_SPEW, "\n");
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return pm1_sts;
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}
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/* Print, clear, and return PM1 status */
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u16 clear_pm1_status(void)
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{
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return print_pm1_status(reset_pm1_status());
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}
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/* Set the PM1 register to events */
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void enable_pm1(u16 events)
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{
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outw(events, ACPI_BASE_ADDRESS + PM1_EN);
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}
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/*
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* Update supplied events in PM1_EN register. This does not disable any already
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* set events.
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*/
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void update_pm1_enable(u16 events)
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{
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u16 pm1_en = read_pm1_enable();
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pm1_en |= events;
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enable_pm1(pm1_en);
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}
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/* Read events set in PM1_EN register. */
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uint16_t read_pm1_enable(void)
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{
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return inw(ACPI_BASE_ADDRESS + PM1_EN);
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}
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/*
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* SMI
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*/
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/* Clear and return SMI status register */
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static u32 reset_smi_status(void)
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const char *const *soc_smi_sts_array(size_t *smi_arr)
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{
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u32 smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS);
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outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS);
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return smi_sts;
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}
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/* Print SMI status bits */
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static u32 print_smi_status(u32 smi_sts)
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{
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static const char * const smi_sts_bits[] = {
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static const char *const smi_sts_bits[] = {
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[2] = "BIOS",
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[3] = "LEGACY_USB",
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[4] = "SLP_SMI",
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@ -199,70 +72,17 @@ static u32 print_smi_status(u32 smi_sts)
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[28] = "ESPI_SMI",
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};
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if (!smi_sts)
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return 0;
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printk(BIOS_DEBUG, "SMI_STS: ");
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print_status_bits(smi_sts, smi_sts_bits);
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printk(BIOS_DEBUG, "\n");
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return smi_sts;
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}
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/* Print, clear, and return SMI status */
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u32 clear_smi_status(void)
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{
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return print_smi_status(reset_smi_status());
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}
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/* Enable SMI event */
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void enable_smi(u32 mask)
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{
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u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
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smi_en |= mask;
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outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
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}
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/* Disable SMI event */
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void disable_smi(u32 mask)
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{
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u32 smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN);
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smi_en &= ~mask;
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outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN);
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*smi_arr = ARRAY_SIZE(smi_sts_bits);
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return smi_sts_bits;
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}
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/*
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* TCO
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*/
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/* Clear TCO status and return events that are enabled and active */
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static u32 reset_tco_status(void)
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const char *const *soc_tco_sts_array(size_t *tco_arr)
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{
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u16 tco1_sts;
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u16 tco2_sts;
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u16 tcobase;
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tcobase = smbus_tco_regs();
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/* TCO Status 2 register*/
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tco2_sts = inw(tcobase + TCO2_STS);
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tco2_sts |= (TCO2_STS_SECOND_TO | TCO2_STS_BOOT);
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outw(tco2_sts, tcobase + TCO2_STS);
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/* TCO Status 1 register*/
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tco1_sts = inw(tcobase + TCO1_STS);
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/* Clear SECOND_TO_STS bit */
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if (tco2_sts & TCO2_STS_SECOND_TO)
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outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);
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return (tco2_sts << 16) | tco1_sts;
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}
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/* Print TCO status bits */
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static u32 print_tco_status(u32 tco_sts)
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{
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static const char * const tco_sts_bits[] = {
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static const char *const tco_sts_bits[] = {
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[0] = "NMI2SMI",
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[1] = "SW_TCO",
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[2] = "TCO_INT",
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@ -279,79 +99,17 @@ static u32 print_tco_status(u32 tco_sts)
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[20] = "SMLINK_SLV"
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};
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if (!tco_sts)
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return 0;
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printk(BIOS_DEBUG, "TCO_STS: ");
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print_status_bits(tco_sts, tco_sts_bits);
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printk(BIOS_DEBUG, "\n");
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return tco_sts;
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*tco_arr = ARRAY_SIZE(tco_sts_bits);
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return tco_sts_bits;
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}
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/* Print, clear, and return TCO status */
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u32 clear_tco_status(void)
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{
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return print_tco_status(reset_tco_status());
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}
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/* Enable TCO SCI */
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void enable_tco_sci(void)
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{
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/* Clear pending events */
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outl(TCOSCI_STS, ACPI_BASE_ADDRESS + GPE0_STS(3));
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/* Enable TCO SCI events */
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enable_gpe(TCOSCI_EN);
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}
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/*
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* GPE0
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*/
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/* Clear a GPE0 status and return events that are enabled and active */
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static u32 reset_gpe(u16 sts_reg, u16 en_reg)
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const char *const *soc_gpe_sts_array(size_t *gpe_arr)
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{
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u32 gpe0_sts = inl(ACPI_BASE_ADDRESS + sts_reg);
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u32 gpe0_en = inl(ACPI_BASE_ADDRESS + en_reg);
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outl(gpe0_sts, ACPI_BASE_ADDRESS + sts_reg);
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/* Only report enabled events */
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return gpe0_sts & gpe0_en;
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}
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/* Print GPE0 status bits */
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static u32 print_gpe_status(u32 gpe0_sts, const char * const bit_names[])
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{
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if (!gpe0_sts)
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return 0;
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printk(BIOS_DEBUG, "GPE0_STS: ");
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print_status_bits(gpe0_sts, bit_names);
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printk(BIOS_DEBUG, "\n");
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return gpe0_sts;
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}
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/* Print GPE0 GPIO status bits */
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static u32 print_gpe_gpio(u32 gpe0_sts, int start)
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{
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if (!gpe0_sts)
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return 0;
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printk(BIOS_DEBUG, "GPE0_STS: ");
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print_gpio_status(gpe0_sts, start);
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printk(BIOS_DEBUG, "\n");
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return gpe0_sts;
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}
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/* Clear all GPE status and return "standard" GPE event status */
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u32 clear_gpe_status(void)
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{
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static const char * const gpe0_sts_3_bits[] = {
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static const char *const gpe_sts_bits[] = {
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[1] = "HOTPLUG",
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[2] = "SWGPE",
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[6] = "TCO_SCI",
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@ -367,72 +125,8 @@ u32 clear_gpe_status(void)
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[18] = "WADT"
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};
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print_gpe_gpio(reset_gpe(GPE0_STS(GPE_31_0), GPE0_EN(GPE_31_0)), 0);
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print_gpe_gpio(reset_gpe(GPE0_STS(GPE_63_32), GPE0_EN(GPE_63_32)), 32);
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print_gpe_gpio(reset_gpe(GPE0_STS(GPE_95_64), GPE0_EN(GPE_95_64)), 64);
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return print_gpe_status(reset_gpe(GPE0_STS(GPE_STD), GPE0_EN(GPE_STD)),
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gpe0_sts_3_bits);
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}
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/* Read and clear GPE status (defined in arch/acpi.h) */
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int acpi_get_gpe(int gpe)
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{
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int bank;
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uint32_t mask, sts;
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struct stopwatch sw;
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int rc = 0;
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if (gpe < 0 || gpe > GPE0_WADT)
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return -1;
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bank = gpe / 32;
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mask = 1 << (gpe % 32);
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/* Wait up to 1ms for GPE status to clear */
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stopwatch_init_msecs_expire(&sw, 1);
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do {
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if (stopwatch_expired(&sw))
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return rc;
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sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank));
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if (sts & mask) {
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outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank));
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rc = 1;
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}
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} while (sts & mask);
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return rc;
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}
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/* Enable all requested GPE */
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void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4)
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{
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outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0));
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outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32));
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outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_95_64));
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outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
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}
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/* Disable all GPE */
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void disable_all_gpe(void)
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{
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enable_all_gpe(0, 0, 0, 0);
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}
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/* Enable a standard GPE */
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void enable_gpe(u32 mask)
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{
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u32 gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
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gpe0_en |= mask;
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outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
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}
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/* Disable a standard GPE */
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void disable_gpe(u32 mask)
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{
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u32 gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
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gpe0_en &= ~mask;
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outl(gpe0_en, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD));
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*gpe_arr = ARRAY_SIZE(gpe_sts_bits);
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return gpe_sts_bits;
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}
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int acpi_sci_irq(void)
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@ -472,7 +166,7 @@ uint8_t *pmc_mmio_regs(void)
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/* 4KiB alignment. */
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reg32 &= ~0xfff;
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return (void *)(uintptr_t)reg32;
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return (void *)(uintptr_t) reg32;
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}
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uint16_t smbus_tco_regs(void)
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@ -486,63 +180,49 @@ uint16_t smbus_tco_regs(void)
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return reg16;
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}
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void poweroff(void)
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uint32_t soc_reset_tco_status(void)
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{
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enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
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u16 tco1_sts;
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u16 tco2_sts;
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u16 tcobase;
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/*
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* Setting SLP_TYP_S5 in PM1 triggers SLP_SMI, which is handled by SMM
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* to transition to S5 state. If halt is called in SMM, then it prevents
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* the SMI handler from being triggered and system never enters S5.
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*/
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if (!ENV_SMM)
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halt();
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tcobase = smbus_tco_regs();
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/* TCO Status 2 register */
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tco2_sts = inw(tcobase + TCO2_STS);
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tco2_sts |= (TCO2_STS_SECOND_TO | TCO2_STS_BOOT);
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outw(tco2_sts, tcobase + TCO2_STS);
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/* TCO Status 1 register */
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tco1_sts = inw(tcobase + TCO1_STS);
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/* Clear SECOND_TO_STS bit */
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if (tco2_sts & TCO2_STS_SECOND_TO)
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outw(tco2_sts & ~TCO2_STS_SECOND_TO, tcobase + TCO2_STS);
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return (tco2_sts << 16) | tco1_sts;
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}
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void pmc_gpe_init(void)
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uintptr_t soc_read_pmc_base(void)
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{
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return (uintptr_t) (pmc_mmio_regs());
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}
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void soc_get_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
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{
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DEVTREE_CONST struct soc_intel_skylake_config *config;
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DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
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uint8_t *pmc_regs;
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uint32_t gpio_cfg;
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uint32_t gpio_cfg_reg;
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const uint32_t gpio_cfg_mask =
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(GPE0_DWX_MASK << GPE0_DW0_SHIFT) |
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(GPE0_DWX_MASK << GPE0_DW1_SHIFT) |
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(GPE0_DWX_MASK << GPE0_DW2_SHIFT);
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/* Look up the device in devicetree */
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DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
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if (!dev || !dev->chip_info) {
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printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
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return;
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}
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config = dev->chip_info;
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pmc_regs = pmc_mmio_regs();
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/* Route the GPIOs to the GPE0 block. Determine that all values
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* are different, and if they aren't use the reset values. */
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gpio_cfg = 0;
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if (config->gpe0_dw0 == config->gpe0_dw1 ||
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config->gpe0_dw1 == config->gpe0_dw2) {
|
||||
printk(BIOS_INFO, "PMC: Using default GPE route.\n");
|
||||
gpio_cfg = read32(pmc_regs + GPIO_CFG);
|
||||
} else {
|
||||
gpio_cfg |= (uint32_t)config->gpe0_dw0 << GPE0_DW0_SHIFT;
|
||||
gpio_cfg |= (uint32_t)config->gpe0_dw1 << GPE0_DW1_SHIFT;
|
||||
gpio_cfg |= (uint32_t)config->gpe0_dw2 << GPE0_DW2_SHIFT;
|
||||
}
|
||||
gpio_cfg_reg = read32(pmc_regs + GPIO_CFG) & ~gpio_cfg_mask;
|
||||
gpio_cfg_reg |= gpio_cfg & gpio_cfg_mask;
|
||||
write32(pmc_regs + GPIO_CFG, gpio_cfg_reg);
|
||||
|
||||
/* Set the routes in the GPIO communities as well. */
|
||||
gpio_route_gpe((gpio_cfg_reg >> GPE0_DW0_SHIFT) & GPE0_DWX_MASK,
|
||||
(gpio_cfg_reg >> GPE0_DW1_SHIFT) & GPE0_DWX_MASK,
|
||||
(gpio_cfg_reg >> GPE0_DW2_SHIFT) & GPE0_DWX_MASK);
|
||||
|
||||
/* Set GPE enables based on devictree. */
|
||||
enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
|
||||
config->gpe0_en_3, config->gpe0_en_4);
|
||||
/* Assign to out variable */
|
||||
*dw0 = config->gpe0_dw0;
|
||||
*dw1 = config->gpe0_dw1;
|
||||
*dw2 = config->gpe0_dw2;
|
||||
}
|
||||
|
||||
int rtc_failure(void)
|
||||
|
||||
Reference in New Issue
Block a user