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mb/amd/birman_plus: Add glinda SOC option for Birman+

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Change-Id: I1efeb7cf1dca31e2a7e17f483f8882925b55e7ea
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
Anand Vaikar
2024-02-27 18:04:41 +05:30
committed by Felix Held
parent adf042f6c6
commit d361163f6b
10 changed files with 421 additions and 9 deletions
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14
src/mainboard/amd/birman_plus/Kconfig
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@@ -20,20 +20,28 @@ config BOARD_AMD_BIRMANPLUS_PHOENIX
select BOARD_AMD_BIRMANPLUS_COMMON
select SOC_AMD_PHOENIX_FSP
config BOARD_AMD_BIRMANPLUS_GLINDA
select BOARD_AMD_BIRMANPLUS_COMMON
select SOC_AMD_GLINDA
if BOARD_AMD_BIRMANPLUS_COMMON
config FMDFILE
default "src/mainboard/amd/birman_plus/chromeos_phoenix.fmd" if CHROMEOS && BOARD_AMD_BIRMANPLUS_PHOENIX
default "src/mainboard/amd/birman_plus/chromeos_glinda.fmd" if CHROMEOS && BOARD_AMD_BIRMANPLUS_GLINDA
default "src/mainboard/amd/birman_plus/board_phoenix.fmd" if BOARD_AMD_BIRMANPLUS_PHOENIX
default "src/mainboard/amd/birman_plus/board_glinda.fmd" if BOARD_AMD_BIRMANPLUS_GLINDA
config MAINBOARD_DIR
default "amd/birman_plus" if BOARD_AMD_BIRMANPLUS_PHOENIX
default "amd/birman_plus" if BOARD_AMD_BIRMANPLUS_PHOENIX || BOARD_AMD_BIRMANPLUS_GLINDA
config MAINBOARD_PART_NUMBER
default "Birmanplus_Phoenix" if BOARD_AMD_BIRMANPLUS_PHOENIX
default "Birmanplus_Glinda" if BOARD_AMD_BIRMANPLUS_GLINDA
config DEVICETREE
default "devicetree_phoenix.cb"
default "devicetree_phoenix.cb" if BOARD_AMD_BIRMANPLUS_PHOENIX
default "devicetree_glinda.cb" if BOARD_AMD_BIRMANPLUS_GLINDA
config BIRMANPLUS_HAVE_MCHP_FW
bool "Have Microchip EC firmware?"
@@ -71,7 +79,7 @@ config RO_REGION_ONLY
string
depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
# Add the EFS and EC to the RO region only
# This is a birman-specific override of soc/amd/(phoenix | glinda)/Kconfig
# This is a birmanplus specific override of soc/amd/(phoenix | glinda)/Kconfig
default "apu/amdfw apu/ecfw"
config CHROMEOS

3
src/mainboard/amd/birman_plus/Kconfig.name
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@@ -2,3 +2,6 @@ comment "BirmanPlus"
config BOARD_AMD_BIRMANPLUS_PHOENIX
bool "-> BirmanPlus for Phoenix SoC"
config BOARD_AMD_BIRMANPLUS_GLINDA
bool "-> BirmanPlus for Glinda SoC"

7
src/mainboard/amd/birman_plus/Makefile.mk
View File

@@ -4,12 +4,13 @@ bootblock-y += bootblock.c
bootblock-y += early_gpio.c
bootblock-y += ec.c
romstage-$(CONFIG_BOARD_AMD_BIRMANPLUS_PHOENIX) += port_descriptors.c
romstage-$(CONFIG_BOARD_AMD_BIRMANPLUS_PHOENIX) += port_descriptors_phoenix.c
romstage-$(CONFIG_BOARD_AMD_BIRMANPLUS_GLINDA) += port_descriptors_glinda.c
ramstage-y += chromeos.c
ramstage-y += gpio.c
ramstage-$(CONFIG_BOARD_AMD_BIRMANPLUS_PHOENIX) += port_descriptors.c
ramstage-$(CONFIG_BOARD_AMD_BIRMANPLUS_PHOENIX) += port_descriptors_phoenix.c
ramstage-$(CONFIG_BOARD_AMD_BIRMANPLUS_GLINDA) += port_descriptors_glinda.c
ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_FP8_LPDDR5.bin),)
APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_FP8_LPDDR5.bin

9
src/mainboard/amd/birman_plus/board_glinda.fmd Normal file
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@@ -0,0 +1,9 @@
FLASH@0xFF000000 16M {
BIOS {
EC_SIG 4K
FMAP 4K
COREBOOT(CBFS)
EC_BODY@15872K 256K
RW_MRC_CACHE 120K
}
}

35
src/mainboard/amd/birman_plus/chromeos_glinda.fmd Normal file
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@@ -0,0 +1,35 @@
FLASH@0xFF000000 16M {
SI_BIOS {
WP_RO 8M {
EC_SIG 4K
RO_VPD(PRESERVE) 16K
RO_SECTION {
FMAP 2K
RO_FRID 64
COREBOOT(CBFS)
GBB 448K
}
}
RW_SECTION_A 3M {
VBLOCK_A 8K
FW_MAIN_A(CBFS)
RW_FWID_A 256
}
RW_SECTION_B 3M {
VBLOCK_B 8K
FW_MAIN_B(CBFS)
RW_FWID_B 256
}
RW_ELOG(PRESERVE) 4K
RW_SHARED 16K {
SHARED_DATA 8K
VBLOCK_DEV 8K
}
RW_VPD(PRESERVE) 8K
RW_NVRAM(PRESERVE) 20K
SMMSTORE(PRESERVE) 64K
RW_LEGACY(CBFS)
EC_BODY@15872K 256K
RW_MRC_CACHE(PRESERVE) 120K
}
}

227
src/mainboard/amd/birman_plus/devicetree_glinda.cb Normal file
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@@ -0,0 +1,227 @@
# SPDX-License-Identifier: GPL-2.0-only
# TODO: Update for birmanplus
chip soc/amd/glinda
register "common_config.espi_config" = "{
.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN,
.generic_io_range[0] = {
.base = 0x3f8,
.size = 8,
},
.generic_io_range[1] = {
.base = 0x600,
.size = 256,
},
.io_mode = ESPI_IO_MODE_QUAD,
.op_freq_mhz = ESPI_OP_FREQ_16_MHZ,
.crc_check_enable = 1,
.alert_pin = ESPI_ALERT_PIN_PUSH_PULL,
.periph_ch_en = 1,
.vw_ch_en = 1,
.oob_ch_en = 1,
.flash_ch_en = 0,
}"
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL |
GPIO_I2C2_SCL | GPIO_I2C3_SCL"
register "i2c[0].early_init" = "1"
register "i2c[1].early_init" = "1"
register "i2c[2].early_init" = "1"
register "i2c[3].early_init" = "1"
# I2C Pad Control RX Select Configuration
register "i2c_pad[0].rx_level" = "I2C_PAD_RX_1_8V"
register "i2c_pad[1].rx_level" = "I2C_PAD_RX_1_8V"
register "i2c_pad[2].rx_level" = "I2C_PAD_RX_1_8V"
register "i2c_pad[3].rx_level" = "I2C_PAD_RX_1_8V"
register "s0ix_enable" = "true"
register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
register "usb_phy_custom" = "1"
register "usb_phy" = "{
.Usb2PhyPort[0] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[1] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[2] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[3] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[4] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb2PhyPort[5] = {
.compdistune = 0x3,
.pllbtune = 0x1,
.pllitune = 0x0,
.pllptune = 0xe,
.sqrxtune = 0x3,
.txfslstune = 0x3,
.txpreempamptune = 0x2,
.txpreemppulsetune = 0x0,
.txrisetune = 0x1,
.txvreftune = 0x3,
.txhsxvtune = 0x3,
.txrestune = 0x2,
},
.Usb3PhyPort[0] = {
.tx_term_ctrl = 0x2,
.rx_term_ctrl = 0x2,
.tx_vboost_lvl_en = 0x0,
.tx_vboost_lvl = 0x5,
},
.Usb3PhyPort[1] = {
.tx_term_ctrl = 0x2,
.rx_term_ctrl = 0x2,
.tx_vboost_lvl_en = 0x0,
.tx_vboost_lvl = 0x5,
},
.Usb3PhyPort[2] = {
.tx_term_ctrl = 0x2,
.rx_term_ctrl = 0x2,
.tx_vboost_lvl_en = 0x0,
.tx_vboost_lvl = 0x5,
},
.ComboPhyStaticConfig[0] = USB_COMBO_PHY_MODE_USB_C,
.ComboPhyStaticConfig[1] = USB_COMBO_PHY_MODE_USB_C,
.BatteryChargerEnable = 0,
.PhyP3CpmP4Support = 0,
}"
register "gpp_clk_config[0]" = "GPP_CLK_REQ"
register "gpp_clk_config[1]" = "GPP_CLK_REQ"
register "gpp_clk_config[2]" = "GPP_CLK_OFF"
register "gpp_clk_config[3]" = "GPP_CLK_REQ"
device domain 0 on
device ref iommu on end
device ref gpp_bridge_0 on end # GBE
device ref gpp_bridge_1 on end # WIFI
device ref gpp_bridge_2 on end # NVMe SSD
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
device ref crypto on end # Crypto Coprocessor
device ref xhci_0 on # USB 3.1 (USB0)
chip drivers/usb/acpi
device ref xhci_0_root_hub on
chip drivers/usb/acpi
device ref usb3_port0 on end
end
chip drivers/usb/acpi
device ref usb2_port0 on end
end
chip drivers/usb/acpi
device ref usb2_port1 on end
end
end
end
end
device ref xhci_1 on # USB 3.1 (USB1)
chip drivers/usb/acpi
device ref xhci_1_root_hub on
chip drivers/usb/acpi
device ref usb3_port2 on end
end
chip drivers/usb/acpi
device ref usb3_port3 on end
end
chip drivers/usb/acpi
device ref usb2_port2 on end
end
chip drivers/usb/acpi
device ref usb2_port3 on end
end
chip drivers/usb/acpi
device ref usb2_port4 on end
end
end
end
end
device ref acp on end # Audio Processor (ACP)
end
device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
device ref xhci_2 on
ops xhci_pci_ops
chip drivers/usb/acpi
register "type" = "UPC_TYPE_HUB"
device usb 0.0 alias xhci_2_root_hub on
chip drivers/usb/acpi
device usb 2.0 alias usb2_port5 on end
end
end
end
end
end
end
device ref i2c_0 on end
device ref i2c_1 on end
device ref i2c_2 on end
device ref i2c_3 on end
device ref uart_0 on end # UART0
end

2
src/mainboard/amd/birman_plus/devicetree_phoenix.cb
View File

@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
# TODO: Update for birman
# TODO: Update for birmanplus
chip soc/amd/phoenix
register "common_config.espi_config" = "{

2
src/mainboard/amd/birman_plus/mainboard.c
View File

@@ -7,7 +7,7 @@
#include <types.h>
#include "gpio.h"
/* TODO: Update for birman */
/* TODO: Update for birmanplus */
/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
accessed via I/O ports 0xc00/0xc01. */

130
src/mainboard/amd/birman_plus/port_descriptors_glinda.c Normal file
View File

@@ -0,0 +1,130 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <console/console.h>
#include <device/i2c_simple.h>
#include <gpio.h>
#include <soc/platform_descriptors.h>
#include <types.h>
/* TODO: Update for birmanplus */
static const fsp_dxio_descriptor birman_dxio_descriptors[] = {
{
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 0,
.end_logical_lane = 0,
.device_number = 2,
.function_number = 1,
.link_speed_capability = GEN3,
.turn_off_unused_lanes = true,
.link_aspm = 2,
.link_hotplug = HOTPLUG_ENHANCED,
.clk_req = CLK_REQ3,
},
{
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 1,
.end_logical_lane = 1,
.device_number = 2,
.function_number = 2,
.link_speed_capability = GEN3,
.turn_off_unused_lanes = true,
.link_aspm = 2,
.link_hotplug = HOTPLUG_ENHANCED,
.clk_req = CLK_REQ1,
},
{
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 2,
.end_logical_lane = 3,
.device_number = 2,
.function_number = 3,
.link_speed_capability = GEN3,
.turn_off_unused_lanes = true,
.link_aspm = 2,
.link_hotplug = HOTPLUG_ENHANCED,
.gpio_group_id = GPIO_27,
.clk_req = CLK_REQ0,
},
};
static fsp_ddi_descriptor birman_ddi_descriptors[] = {
{ /* DDI0 - eDP */
.connector_type = DDI_EDP,
.aux_index = DDI_AUX1,
.hdp_index = DDI_HDP1
},
{ /* DDI1 - HDMI/DP */
.connector_type = DDI_HDMI,
.aux_index = DDI_AUX2,
.hdp_index = DDI_HDP2
},
{ /* DDI2 - DP (type C) */
.connector_type = DDI_DP_W_TYPEC,
.aux_index = DDI_AUX3,
.hdp_index = DDI_HDP3,
},
{ /* DDI3 - DP (type C) */
.connector_type = DDI_DP_W_TYPEC,
.aux_index = DDI_AUX4,
.hdp_index = DDI_HDP4,
},
{ /* DDI4 - DP (type C) */
.connector_type = DDI_DP_W_TYPEC,
.aux_index = DDI_AUX5,
.hdp_index = DDI_HDP5,
}
};
static uint8_t get_ddi1_type(void)
{
const uint8_t eeprom_i2c_bus = 2;
const uint8_t eeprom_i2c_address = 0x55;
const uint16_t eeprom_connector_type_offset = 2;
uint8_t eeprom_connector_type_data[2];
uint16_t connector_type;
if (i2c_2ba_read_bytes(eeprom_i2c_bus, eeprom_i2c_address,
eeprom_connector_type_offset, eeprom_connector_type_data,
sizeof(eeprom_connector_type_data))) {
printk(BIOS_NOTICE,
"Display connector type couldn't be determined. Disabling DDI1.\n");
return DDI_UNUSED_TYPE;
}
connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8;
switch (connector_type) {
case 0x0c:
printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n");
return DDI_HDMI;
case 0x13:
printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n");
return DDI_DP;
case 0x14:
printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n");
return DDI_EDP;
case 0x17:
printk(BIOS_DEBUG, "Configuring DDI1 as USB-C.\n");
return DDI_DP_W_TYPEC;
default:
printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n",
connector_type);
return DDI_UNUSED_TYPE;
}
}
void mainboard_get_dxio_ddi_descriptors(
const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
{
birman_ddi_descriptors[1].connector_type = get_ddi1_type();
*dxio_descs = birman_dxio_descriptors;
*dxio_num = ARRAY_SIZE(birman_dxio_descriptors);
*ddi_descs = birman_ddi_descriptors;
*ddi_num = ARRAY_SIZE(birman_ddi_descriptors);
}

1
src/mainboard/amd/birman_plus/port_descriptors.c → src/mainboard/amd/birman_plus/port_descriptors_phoenix.c
View File

@@ -4,7 +4,6 @@
#include <device/i2c_simple.h>
#include <gpio.h>
#include <soc/platform_descriptors.h>
#include <soc/soc_util.h>
#include <types.h>
#define phx_mxm_dxio_descriptor { \