mb/pcengines: Remove unneeded includes and dead code

Fix coding style.

Change-Id: Id13c0ee284293c0c06d46c75c850bc7e81cfc1f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>

src/mainboard/pcengines/alix1c/devicetree.cb

@@ -1,6 +1,6 @@
 chip northbridge/amd/lx
 	device domain 0 on
-	device pci 1.0 on end
+		device pci 1.0 on end
 		device pci 1.1 on end
 		chip southbridge/amd/cs5536
 			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
@@ -25,7 +25,7 @@ chip northbridge/amd/lx
 			register "com2_address" = "0x2F8"
 			register "com2_irq" = "3"
 			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-				device pci f.0 on	# ISA Bridge
+			device pci f.0 on	# ISA Bridge
 				chip superio/winbond/w83627hf
 					device pnp 2e.0 off #  Floppy
 						io 0x60 = 0x3f0

src/mainboard/pcengines/alix1c/irq_tables.c

@@ -14,9 +14,6 @@
 */
 
 #include <arch/pirq_routing.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include "southbridge/amd/cs5536/cs5536.h"
 
 /* Platform IRQs */
 #define PIRQA 11
@@ -53,15 +50,15 @@
  *
  * The only devices that interrupt are:
  *
- * What         Device  IRQ     PIN     PIN WIRED TO
+ * What		Device  IRQ	PIN	PIN WIRED TO
  * -------------------------------------------------
- * AES          00:01.2 0a      01      A       A
+ * AES		00:01.2 0a	01	A	A
- * 3VPCI        00:0c.0 0a      01      A       A
+ * 3VPCI	00:0c.0 0a	01	A	A
- * eth0 	00:0d.0 0b      01      A       B
+ * eth0		00:0d.0 0b	01	A	B
- * mpci 	00:0e.0 0a      01      A       A
+ * mpci		00:0e.0 0a	01	A	A
- * usb          00:0f.3 0b      02      B       B
+ * usb		00:0f.3 0b	02	B	B
- * usb          00:0f.4 0b      04      D       D
+ * usb		00:0f.4 0b	04	D	D
- * usb          00:0f.5 0b      04      D       D
+ * usb		00:0f.5 0b	04	D	D
  *
  * The only swizzled interrupt is eth0, where INTA is wired to interrupt controller line B.
  */
@@ -71,7 +68,7 @@ static const struct irq_routing_table intel_irq_routing_table = {
 	PIRQ_VERSION,
 	32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
 	0x00,			/* Where the interrupt router lies (bus) */
-	(0x0F << 3) | 0x0,      /* Where the interrupt router lies (dev) */
+	(0x0F << 3) | 0x0,	/* Where the interrupt router lies (dev) */
 	0x00,			/* IRQs devoted exclusively to PCI usage */
 	0x100B,			/* Vendor */
 	0x002B,			/* Device */

src/mainboard/pcengines/apu1/acpi/gpe.asl

@@ -72,7 +72,7 @@ Scope(\_GPE) {	/* Start Scope GPE */
 		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
 		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 	}
-} 	/* End Scope GPE */
+}	/* End Scope GPE */
 
 /* Contains the GPEs for USB overcurrent */
 #include "usb_oc.asl"

src/mainboard/pcengines/apu1/acpi/sleep.asl

@@ -49,7 +49,7 @@ Method(\_PTS, 1) {
 
 	/* On older chips, clear PciExpWakeDisEn */
 	/*if (LLessEqual(\_SB.SBRI, 0x13)) {
-	*    	Store(0,\_SB.PWDE)
+	*	Store(0,\_SB.PWDE)
 	*}
 	*/
 

src/mainboard/pcengines/apu2/acpi/gpe.asl

@@ -64,4 +64,4 @@ Scope(\_GPE) {	/* Start Scope GPE */
 		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
 		Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
 	}
-} 	/* End Scope GPE */
+}	/* End Scope GPE */

src/mainboard/pcengines/apu2/dsdt.asl

@@ -46,7 +46,7 @@ DefinitionBlock (
 
 	/* System Bus */
 	Scope(\_SB) { /* Start \_SB scope */
-	 	/* global utility methods expected within the \_SB scope */
+		/* global utility methods expected within the \_SB scope */
 		#include <arch/x86/acpi/globutil.asl>
 
 		/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */

src/mainboard/pcengines/apu2/mptable.c

@@ -14,54 +14,11 @@
  * GNU General Public License for more details.
  */
 
-#include <console/console.h>
 #include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <arch/io.h>
 #include <arch/ioapic.h>
-#include <string.h>
 #include <stdint.h>
-#include <arch/cpu.h>
-#include <cpu/x86/lapic.h>
 #include <southbridge/amd/common/amd_pci_util.h>
 
-#if 0
-u8 picr_data[FCH_INT_TABLE_SIZE] = {
-	0x03,0x03,0x05,0x07,0x0B,0x0A,0x1F,0x1F,  /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/
-	0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,  /* 08 - 0F */
-	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,  /* 10 - 17 */
-	0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 18 - 1F */
-	0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,  /* 20 - 27 */
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 28 - 2F */
-	0x05,0x1F,0x05,0x1F,0x04,0x1F,0x1F,0x1F,  /* 30 - 37 */
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 38 - 3F */
-	0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,  /* 40 - 47 */
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 48 - 4F */
-//	0x03,0x04,0x05,0x07,0x00,0x00,0x00,0x00,  /* 50 - 57 */
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 50 - 57 */
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 58 - 5F */
-	0x00,0x00,0x1F 							   /* 60 - 62 */
-};
-u8 intr_data[FCH_INT_TABLE_SIZE] = {
-	0x10,0x10,0x12,0x13,0x14,0x15,0x1F,0x1F,  /* 00 - 07 : INTA - INTF and 2 reserved dont map 4*/
-	0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,  /* 08 - 0F */
-	0x09,0x1F,0x1F,0x1F,0x1F,0x1f,0x1F,0x10,  /* 10 - 17 */
-	0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 18 - 1F */
-	0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,  /* 20 - 27 */
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 28 - 2F */
-	0x12,0x1f,0x12,0x1F,0x12,0x1F,0x1F,0x00,  /* 30 - 37 */
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 38 - 3F */
-	0x1f,0x13,0x00,0x00,0x00,0x00,0x00,0x00,  /* 40 - 47 */
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 48 - 4F */
-//	0x10,0x11,0x12,0x13,0x00,0x00,0x00,0x00,  /* 50 - 57 */
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 50 - 57 */
-	0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,  /* 58 - 5F */
-	0x00,0x00,0x1F 							   /* 60 - 62 */
-};
-
-#endif
-
-
 static void *smp_write_config_table(void *v)
 {
 	struct mp_config_table *mc;