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haswell: Add function to retrieve SPD addresses

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And use it instead of directly writing to the MRC struct.

Change-Id: I7f04db29a08512c1a8b2b2300dba71cb3b84a5c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
This commit is contained in:
Angel Pons 2020-07-03 23:52:34 +02:00
parent 3ac92b7c93
commit d37b7d89fd
9 changed files with 61 additions and 20 deletions
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13
src/mainboard/asrock/b85m_pro4/romstage.c
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@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h> #include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/pch.h>
@ -16,12 +17,16 @@ void mainboard_config_rcba(void)
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
} }
void mb_get_spd_map(uint8_t spd_map[4])
{
spd_map[0] = 0xa0;
spd_map[1] = 0xa2;
spd_map[2] = 0xa4;
spd_map[3] = 0xa6;
}
void mainboard_fill_pei_data(struct pei_data *pei_data) void mainboard_fill_pei_data(struct pei_data *pei_data)
{ {
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[1] = 0xa2;
pei_data->spd_addresses[2] = 0xa4;
pei_data->spd_addresses[3] = 0xa6;
pei_data->ec_present = 0; pei_data->ec_present = 0;
pei_data->gbe_enable = 1; pei_data->gbe_enable = 1;

9
src/mainboard/asrock/h81m-hds/romstage.c
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@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h> #include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/pch.h>
@ -16,10 +17,14 @@ void mainboard_config_rcba(void)
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
} }
void mb_get_spd_map(uint8_t spd_map[4])
{
spd_map[0] = 0xa0;
spd_map[2] = 0xa4;
}
void mainboard_fill_pei_data(struct pei_data *pei_data) void mainboard_fill_pei_data(struct pei_data *pei_data)
{ {
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[2] = 0xa4;
pei_data->ec_present = 0; pei_data->ec_present = 0;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {

9
src/mainboard/google/beltino/romstage.c
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@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h> #include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/pch.h>
@ -39,10 +40,14 @@ void mainboard_config_rcba(void)
RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */
} }
void mb_get_spd_map(uint8_t spd_map[4])
{
spd_map[0] = 0xa0;
spd_map[2] = 0xa4;
}
void mainboard_fill_pei_data(struct pei_data *pei_data) void mainboard_fill_pei_data(struct pei_data *pei_data)
{ {
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[2] = 0xa4;
pei_data->ec_present = 0; pei_data->ec_present = 0;
pei_data->dq_pins_interleaved = 1; pei_data->dq_pins_interleaved = 1;
pei_data->usb_xhci_on_resume = 1; pei_data->usb_xhci_on_resume = 1;

9
src/mainboard/google/slippy/romstage.c
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@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h> #include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/pch.h>
@ -40,10 +41,14 @@ void mainboard_config_rcba(void)
RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */
} }
void mb_get_spd_map(uint8_t spd_map[4])
{
spd_map[0] = 0xff;
spd_map[2] = 0xff;
}
void mainboard_fill_pei_data(struct pei_data *pei_data) void mainboard_fill_pei_data(struct pei_data *pei_data)
{ {
pei_data->spd_addresses[0] = 0xff;
pei_data->spd_addresses[2] = 0xff;
pei_data->ec_present = 1; pei_data->ec_present = 1;
pei_data->usb_xhci_on_resume = 1; pei_data->usb_xhci_on_resume = 1;

13
src/mainboard/intel/baskingridge/romstage.c
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@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h> #include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/pch.h>
@ -40,12 +41,16 @@ void mainboard_config_rcba(void)
RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
} }
void mb_get_spd_map(uint8_t spd_map[4])
{
spd_map[0] = 0xa0;
spd_map[1] = 0xa2;
spd_map[2] = 0xa4;
spd_map[3] = 0xa6;
}
void mainboard_fill_pei_data(struct pei_data *pei_data) void mainboard_fill_pei_data(struct pei_data *pei_data)
{ {
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[1] = 0xa2;
pei_data->spd_addresses[2] = 0xa4;
pei_data->spd_addresses[3] = 0xa6;
pei_data->ec_present = 0; pei_data->ec_present = 0;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {

8
src/mainboard/lenovo/t440p/romstage.c
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@ -40,10 +40,14 @@ void mb_late_romstage_setup(void)
} }
} }
void mb_get_spd_map(uint8_t spd_map[4])
{
spd_map[0] = 0xa0;
spd_map[2] = 0xa2;
}
void mainboard_fill_pei_data(struct pei_data *pei_data) void mainboard_fill_pei_data(struct pei_data *pei_data)
{ {
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[2] = 0xa2;
pei_data->ec_present = 1; pei_data->ec_present = 1;
pei_data->gbe_enable = 1; pei_data->gbe_enable = 1;

13
src/mainboard/supermicro/x10slm-f/romstage.c
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@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <stdint.h>
#include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h> #include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/pch.h>
@ -16,12 +17,16 @@ void mainboard_config_rcba(void)
RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD);
} }
void mb_get_spd_map(uint8_t spd_map[4])
{
spd_map[0] = 0xa0;
spd_map[1] = 0xa2;
spd_map[2] = 0xa4;
spd_map[3] = 0xa6;
}
void mainboard_fill_pei_data(struct pei_data *pei_data) void mainboard_fill_pei_data(struct pei_data *pei_data)
{ {
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[1] = 0xa2;
pei_data->spd_addresses[2] = 0xa4;
pei_data->spd_addresses[3] = 0xa6;
pei_data->ec_present = 0; pei_data->ec_present = 0;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {

4
src/northbridge/intel/haswell/raminit.h
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@ -3,11 +3,15 @@
#ifndef RAMINIT_H #ifndef RAMINIT_H
#define RAMINIT_H #define RAMINIT_H
#include <stdint.h>
#include "pei_data.h" #include "pei_data.h"
/* Optional function to copy SPD data for on-board memory */ /* Optional function to copy SPD data for on-board memory */
void copy_spd(struct pei_data *peid); void copy_spd(struct pei_data *peid);
/* Mainboard callback to fill in the SPD addresses in MRC format */
void mb_get_spd_map(uint8_t spd_map[4]);
/* Necessary function to initialize pei_data with mainboard-specific settings */ /* Necessary function to initialize pei_data with mainboard-specific settings */
void mainboard_fill_pei_data(struct pei_data *pei_data); void mainboard_fill_pei_data(struct pei_data *pei_data);

3
src/northbridge/intel/haswell/romstage.c
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@ -87,6 +87,9 @@ void mainboard_romstage_entry(void)
/* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */ /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */
pei_data.boot_mode = wake_from_s3 ? 2 : 0; pei_data.boot_mode = wake_from_s3 ? 2 : 0;
/* Obtain the SPD addresses from mainboard code */
mb_get_spd_map(pei_data.spd_addresses);
/* Calculate unimplemented DIMM slots for each channel */ /* Calculate unimplemented DIMM slots for each channel */
pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0); pei_data.dimm_channel0_disabled = make_channel_disabled_mask(&pei_data, 0);
pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1); pei_data.dimm_channel1_disabled = make_channel_disabled_mask(&pei_data, 1);