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Fall back to pre-broken settings and setup for GX2.

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We lost a few things, but this is still worth it.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
2006-05-02 03:07:11 +00:00
parent ae3cbe951b
commit d3ba4aaa24
12 changed files with 361 additions and 324 deletions
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3
src/southbridge/amd/cs5536/cs5536.c
View File

@@ -29,13 +29,11 @@ static void southbridge_enable(struct device *dev)
msr.lo = sb->lpc_serirq_enable;
msr.hi = 0;
wrmsr(MDD_LPC_SIRQ, msr);
printk_debug("Enabled LPC SERIRQ 0x%x\n", msr.lo);
}
if (sb->lpc_irq) {
msr.lo = sb->lpc_irq;
msr.hi = 0;
wrmsr(MDD_IRQM_LPC, msr);
printk_debug("Enabled lpc irq values 0x%x\n", msr.lo);
}
if (sb->enable_gpio0_inta){
@@ -49,7 +47,6 @@ static void southbridge_enable(struct device *dev)
/* magic stuff */
outl(0x3081, GPIOL_INPUT_INVERT_ENABLE);
outl(GPIOL_0_SET, GPIO_MAPPER_X);
printk_debug("Enabled GPIO0 INTa\n");
}

2
src/southbridge/amd/cs5536/cs5536_early_setup.c
View File

@@ -165,7 +165,7 @@ static int cs5536_setup_onchipuart(void)
* MSR 0x51400014 bit 18:16
* 3. Enable UART controller
* MSR 0x5140003A bit 0, 1
* 4. IRQ routing on IRQ Mapper (before loading OS)
* 4. IRQ routing on IRQ Mapper
* MSR 0x51400021 bit [27:24]
*/
msr_t msr;