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arch/x86: Relocate GDT in verstage, romstage, and postcar

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In each stage keep GDT in the code region. This accommodates
platforms, such as glk, that are executing out of CAR. The
gdt is small and loading it is trivial so just do it unconditionally
instead of introducing another Kconfig.

BUG=b:78656686

Change-Id: I01ded6e9b358b23e04d92bef5263bfe8c2a5ec5a
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This commit is contained in:
Hannah Williams
2018-04-27 09:09:04 -07:00
committed by Aaron Durbin
parent 0f9af5500e
commit d3c0c0c318
5 changed files with 59 additions and 34 deletions
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31
src/cpu/x86/32bit/entry32.inc
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@@ -16,38 +16,9 @@
#include <arch/rom_segs.h>
#include <cpu/x86/post_code.h>
#include <rules.h>
#include <arch/x86/gdt_init.S>
.code32
/* This is the GDT for the ROM stage part of coreboot. It
* is different from the RAM stage GDT which is defined in
* c_start.S
*/
.align 4
.globl gdtptr
gdt:
gdtptr:
.word gdt_end - gdt -1 /* compute the table limit */
.long gdt /* we know the offset */
.word 0
/* selgdt 0x08, flat code segment */
.word 0xffff, 0x0000
.byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */
/* selgdt 0x10,flat data segment */
.word 0xffff, 0x0000
.byte 0x00, 0x93, 0xcf, 0x00
/* selgdt 0x18, flat code segment (64-bit) */
.word 0xffff, 0x0000
.byte 0x00, 0x9b, 0xaf, 0x00
gdt_end:
/*
* When we come here we are in protected mode. We expand
* the stack and copies the data segment from ROM to the