tegra124/nyan: rougly stable code base
nyan: Clock setup. Reviewed-on: https://chromium-review.googlesource.com/172106 (cherry picked from commit 3697b6454c0aceebcf735436de90ba2441c9b7b1) tegra124: Call into the mainboard bootblock init if one exists. Reviewed-on: https://chromium-review.googlesource.com/172581 (cherry picked from commit 3a0cd48a0d1a9ce6b32ed614cd81fb81f5f82aec) nyan: Add a mainboard specific bootblock. Reviewed-on: https://chromium-review.googlesource.com/172582 (cherry picked from commit a83d065d660a26fe71ed79879c25f84a1b669f69) nyan: tegra124: Redestribute the clock code between the mainboard and soc. Reviewed-on: https://chromium-review.googlesource.com/172583 (cherry picked from commit ea703137fc37befa7d5a65afc982e298a0daca1b) nyan: Initialize the i2c pins and controllers. Reviewed-on: https://chromium-review.googlesource.com/172584 (cherry picked from commit 9c10a3074ef834688fea46c03551c2e3e54e44a8) nyan: Initialize the PMIC. Reviewed-on: https://chromium-review.googlesource.com/172585 (cherry picked from commit f6be8b0e607e05b73b5e4a84afcf04c879eee88a) tegra124: add a chip.h and use it in NYAN Reviewed-on: https://chromium-review.googlesource.com/172773 (cherry picked from commit 4dd5f1f091f2dcae5ce38203bb86c62994609f8f) tegra: Reorder GPIO register accesses to avoid glitching Reviewed-on: https://chromium-review.googlesource.com/172730 (cherry picked from commit 61bedbf0f839e19b284d21af2ad10f2ff15e17d5) tegra: Turn GPIO wrappers into macros to make them easier to write Reviewed-on: https://chromium-review.googlesource.com/172731 (cherry picked from commit 94550fdfa5a8005d2e6a313041de212ab7ac470c) tegra: Change GPIO functions to allow variable arguments Reviewed-on: https://chromium-review.googlesource.com/172916 (cherry picked from commit e95ccd984f718a04b6067ff6ad5049a2cd74466d) tegra124: Implement starting up the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/172917 (cherry picked from commit 7c5169a197310e18a3df0f176c499669e3c2bda3) tegra: Simplify the I2C constants. Reviewed-on: https://chromium-review.googlesource.com/172953 (cherry picked from commit 130a07c86dfa5ba5ac4580f29db927c91f045c76) tegra124: Fix SPI base addresses Reviewed-on: https://chromium-review.googlesource.com/173322 (cherry picked from commit da808e46919ebd3b9f2377a5889f0d5f10b92357) tegra124: Scrub the clock constants. Reviewed-on: https://chromium-review.googlesource.com/172954 (cherry picked from commit 9305ff0696a6d556a97f928b8683770833a309a4) tegra124: add DMA support Reviewed-on: https://chromium-review.googlesource.com/172951 (cherry picked from commit 4d2a5a56b922ac37d2326d7b139697567aac37b8) tegra124: add basic SPI driver Reviewed-on: https://chromium-review.googlesource.com/172952 (cherry picked from commit 5f861f13c7fd2dd881f3cbd0f1b4d4a9994ce429) tegra124: Add an assembly stub which is run first on the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/173541 (cherry picked from commit e142b9572a89f43fe984c4fc87e3203f380ff4de) nyan: tegra124: Set up dynamic cbmem. Reviewed-on: https://chromium-review.googlesource.com/173542 (cherry picked from commit b6e1a70103446abb5c3440f145617e6566879c6f) tegra124: Add an soc.c which sets up the chip operations and memory resource. Reviewed-on: https://chromium-review.googlesource.com/173543 (cherry picked from commit af49a5bd1f589cf053c4808510138aae26e20db4) tegra124: extend chip.h to include video settings Reviewed-on: https://chromium-review.googlesource.com/173600 (cherry picked from commit 87687633a2116f58fad7333b3b639cee9089ad29) tegra124 and nyan: fill in the devicetree a bit more, add defines Reviewed-on: https://chromium-review.googlesource.com/173684 (cherry picked from commit c107eaca3dea42be89f61690d0d6cb2181acb147) tegra124: clean-ups for SPI driver Reviewed-on: https://chromium-review.googlesource.com/173599 (cherry picked from commit 1e2f9fd442ea336bf0663c3c8ea51f771e21beb7) tegra124: add a #define for DMA alignment size Reviewed-on: https://chromium-review.googlesource.com/173638 (cherry picked from commit f9dc2a8d8016fa7db974fb6cb01c3275e26832af) tegra124: Add FIFO transmit functions to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173639 (cherry picked from commit 97e61f36ad96ce2f9b12a7ef765ee73d3f4285f7) tegra124: clean-ups for DMA driver Reviewed-on: https://chromium-review.googlesource.com/173598 (cherry picked from commit 750c0a5d6942748dd21f3a3f884ad94a561e86e0) tegra124: early display and display code. Reviewed-on: https://chromium-review.googlesource.com/173622 (cherry picked from commit 651c7ab96b1f136865e4673a120de7afc1218558) tegra124: Move transfer size handling to spi_xfer() Reviewed-on: https://chromium-review.googlesource.com/173680 (cherry picked from commit 4a9b7b47b3c09d70063ea843054ffef98f554621) tegra124: strict error detection and reporting for SPI Reviewed-on: https://chromium-review.googlesource.com/173681 (cherry picked from commit c056fa954e1dab40a56faec6c50385763a2eb010) tegra124: add thread-friendly delays to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173648 (cherry picked from commit c1a321c8f61942801627f895c5db74c518e2aa8e) Tegra124: Take the SPI1 controller out of reset and enable its clock. Reviewed-on: https://chromium-review.googlesource.com/173787 (cherry picked from commit c026a3fb861e157f1e17a121fc2ef70b903f36f2) tegra124: add two more clock setting values Reviewed-on: https://chromium-review.googlesource.com/173772 (cherry picked from commit 7d79d7dd9f0c1fd7127a7ba41652d809ccff7a57) nyan: Set up the ChromeOS related GPIOs and SPI bus 1 which goes to the EC. Reviewed-on: https://chromium-review.googlesource.com/173788 (cherry picked from commit ff172bfe30f75983a1e8efa2ead0a4519583d0a8) tegra124: Add some stub functions to the Tegra SPI driver. Reviewed-on: https://chromium-review.googlesource.com/173789 (cherry picked from commit 8bc527aa4afd301c046b0e844c7fa400630af0d2) tegra124: Build source files into the various stges needed by CONFIG_CHROMEOS. Reviewed-on: https://chromium-review.googlesource.com/173790 (cherry picked from commit 86a6423b668ca912295c47d8c6e3ef6c6f8c6084) nyan: Implement the code which reads GPIOs for ChromeOS. Reviewed-on: https://chromium-review.googlesource.com/173791 (cherry picked from commit 4c394dfbce762574fc79edcb6e4ac6bf346e48a3) nyan: Enable the CHROMEOS and ChromeOS EC related kconfig options. Reviewed-on: https://chromium-review.googlesource.com/173792 (cherry picked from commit 2845a4487159aa4b1dba58d977f52c449574fc8e) Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks. Reviewed-on: https://chromium-review.googlesource.com/173793 (cherry picked from commit c238b87bcd9d35afd828476d6ee88322ac5d0f88) tegra124: fix clear_fifo_status() in SPI driver Reviewed-on: https://chromium-review.googlesource.com/173738 (cherry picked from commit f415d2c0aaffc0f1a3592551a2db782d538f8f4f) ARM: Include stdint.h in cpu.h. Reviewed-on: https://chromium-review.googlesource.com/173774 (cherry picked from commit f1930faea3f14b2a2560a6c4058ef38532b6f1a6) tegra124: When setting up the main CPU, set its CPSR appropriately. Reviewed-on: https://chromium-review.googlesource.com/173775 (cherry picked from commit bc2ba9c15cfd22aeaca4f80b1d13a8b5e0178ead) tegra124: fix wrong names in clk_rst.h Reviewed-on: https://chromium-review.googlesource.com/173955 (cherry picked from commit 19dd9c85e4a3d1f77b23828bcbdd4bd8c2688b8d) tegra124: Fix up the PLLX divider table. Reviewed-on: https://chromium-review.googlesource.com/173778 (cherry picked from commit 3362cf3a7d6f5eaec879dda42323345922f6df17) tegra124: clock: Get rid of cpcon and dccon. Reviewed-on: https://chromium-review.googlesource.com/173779 (cherry picked from commit 08626ffac4a7e9ea3d4738af87e9e4cced7be2c7) Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus. Reviewed-on: https://chromium-review.googlesource.com/173953 (cherry picked from commit a2df8f3a9c9c54c62d6ff37d3baff1d30ee6d355) armv7: expose dcache_line_bytes() in cache API Reviewed-on: https://chromium-review.googlesource.com/173975 (cherry picked from commit 6727f65702c7668fcb33848b4113bc3d3cc04e12) libpayload: expose dcache_line_bytes() in ARM cache API Reviewed-on: https://chromium-review.googlesource.com/174099 (cherry picked from commit 9387b02dff85b42944d95c3bccf59059c93fb4a9) armv4: add a stub for dcache_line_bytes() Reviewed-on: https://chromium-review.googlesource.com/173976 (cherry picked from commit 924f61ea895b9268c716791466637009bbac6469) tegra124: Base early UART on CLK_M to enable debugging of PLL init code Reviewed-on: https://chromium-review.googlesource.com/174339 (cherry picked from commit 8d9387432f0a0d9b257b040304238e543cced1aa) tegra124: Add additional PLLs and redesign the divisor table Reviewed-on: https://chromium-review.googlesource.com/174380 (cherry picked from commit f6a5f5c4562f1ca733505717c175be00413f2384) Squashed 49 commits for tegra124/nyan that included a lot of churn on different pieces. Change-Id: I00e8f5b74e835e01b28ca2e9c4af3709c9363d56 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6869 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
Gabe Black
committed by
Isaac Christensen
Isaac Christensen
parent
35c0f439fc
commit
d40be1107c
236
src/soc/nvidia/tegra124/dma.c
Normal file
236
src/soc/nvidia/tegra124/dma.c
Normal file
@@ -0,0 +1,236 @@
|
||||
/*
|
||||
* (C) Copyright 2010,2011
|
||||
* NVIDIA Corporation <www.nvidia.com>
|
||||
* Copyright 2013 Google Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <inttypes.h>
|
||||
#include <stddef.h>
|
||||
#include <stdlib.h>
|
||||
#include <console/console.h>
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <soc/addressmap.h>
|
||||
|
||||
#include "dma.h"
|
||||
|
||||
/*
|
||||
* Note: Many APB DMA controller registers are laid out such that each
|
||||
* bit controls or represents the status for the corresponding channel.
|
||||
* So we will not bother to list each individual bit in this case.
|
||||
*/
|
||||
#define APBDMA_COMMAND_GEN (1 << 31)
|
||||
|
||||
#define APBDMA_CNTRL_REG_COUNT_VALUE_MASK 0xffff
|
||||
#define APBDMA_CNTRL_REG_COUNT_VALUE_SHIFT 0
|
||||
|
||||
struct apb_dma {
|
||||
u32 command; /* 0x00 */
|
||||
u32 status; /* 0x04 */
|
||||
u32 rsvd1[2];
|
||||
u32 cntrl_reg; /* 0x10 */
|
||||
u32 irq_sta_cpu; /* 0x14 */
|
||||
u32 irq_sta_cop; /* 0x18 */
|
||||
u32 irq_mask; /* 0x1c */
|
||||
u32 irq_mask_set; /* 0x20 */
|
||||
u32 irq_mask_clr; /* 0x24 */
|
||||
u32 trig_reg; /* 0x28 */
|
||||
u32 channel_trig_reg; /* 0x2c */
|
||||
u32 dma_status; /* 0x30 */
|
||||
u32 channel_en_reg; /* 0x34 */
|
||||
u32 security_reg; /* 0x38 */
|
||||
u32 channel_swid; /* 0x3c */
|
||||
u32 rsvd[1];
|
||||
u32 chan_wt_reg0; /* 0x44 */
|
||||
u32 chan_wt_reg1; /* 0x48 */
|
||||
u32 chan_wt_reg2; /* 0x4c */
|
||||
u32 chan_wr_reg3; /* 0x50 */
|
||||
u32 channel_swid1; /* 0x54 */
|
||||
} __attribute__((packed));
|
||||
struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE;
|
||||
|
||||
/*
|
||||
* Naming in the doc included a superfluous _CHANNEL_n_ for
|
||||
* each entry and was left out for the sake of conciseness.
|
||||
*/
|
||||
#define APBDMACHAN_CSR_ENB (1 << 31)
|
||||
#define APBDMACHAN_CSR_IE_EOC (1 << 30)
|
||||
#define APBDMACHAN_CSR_HOLD (1 << 29)
|
||||
#define APBDMACHAN_CSR_DIR (1 << 28)
|
||||
#define APBDMACHAN_CSR_ONCE (1 << 27)
|
||||
#define APBDMACHAN_CSR_FLOW (1 << 21)
|
||||
#define APBDMACHAN_CSR_REQ_SEL_MASK 0x1f
|
||||
#define APBDMACHAN_CSR_REQ_SEL_SHIFT 16
|
||||
|
||||
#define APBDMACHAN_STA_BSY (1 << 31)
|
||||
#define APBDMACHAN_STA_ISE_EOC (1 << 30)
|
||||
#define APBDMACHAN_STA_HALT (1 << 29)
|
||||
#define APBDMACHAN_STA_PING_PONG_STA (1 << 28)
|
||||
#define APBDMACHAN_STA_DMA_ACTIVITY (1 << 27)
|
||||
#define APBDMACHAN_STA_CHANNEL_PAUSE (1 << 26)
|
||||
|
||||
#define APBDMACHAN_CSRE_CHANNEL_PAUSE (1 << 31)
|
||||
#define APBDMACHAN_CSRE_TRIG_SEL_MASK 0x3f
|
||||
#define APBDMACHAN_CSRE_TRIG_SEL_SHIFT 14
|
||||
|
||||
#define APBDMACHAN_AHB_PTR_MASK (0x3fffffff)
|
||||
#define APBDMACHAN_AHB_PTR_SHIFT 2
|
||||
|
||||
#define APBDMACHAN_AHB_SEQ_INTR_ENB (1 << 31)
|
||||
#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_MASK 0x7
|
||||
#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_SHIFT 28
|
||||
#define APBDMACHAN_AHB_SEQ_AHB_DATA_SWAP (1 << 27)
|
||||
#define APBDMACHAN_AHB_SEQ_AHB_BURST_MASK 0x7
|
||||
#define APBDMACHAN_AHB_SEQ_AHB_BURST_SHIFT 24
|
||||
#define APBDMACHAN_AHB_SEQ_DBL_BUF (1 << 19)
|
||||
#define APBDMACHAN_AHB_SEQ_WRAP_MASK 0x7
|
||||
#define APBDMACHAN_AHB_SEQ_WRAP_SHIFT 16
|
||||
|
||||
#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_MASK 0x7
|
||||
#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_SHIFT 28
|
||||
|
||||
#define APBDMACHAN_APB_PTR_MASK 0x3fffffff
|
||||
#define APBDMACHAN_APB_PTR_SHIFT 2
|
||||
|
||||
#define APBDMACHAN_APB_SEQ_APB_BUS_WIDTH_MASK 0x7
|
||||
#define APBDMACHAN_APB_SEQ_APB_BUS_WIDTH_SHIFT 28
|
||||
#define APBDMACHAN_APB_SEQ_APB_DATA_SWAP (1 << 27)
|
||||
#define APBDMACHAN_APB_SEQ_APB_ADDR_WRAP_MASK 0x7
|
||||
#define APBDMACHAN_APB_SEQ_APB_ADDR_WRAP_SHIFT 16
|
||||
|
||||
#define APBDMACHAN_WORD_TRANSFER_
|
||||
|
||||
#define APBDMACHAN_WORD_TRANSFER_MASK 0x0fffffff
|
||||
#define APBDMACHAN_WORD_TRANSFER_SHIFT 2
|
||||
|
||||
#define APB_DMA_OFFSET(n) \
|
||||
(struct apb_dma_channel_regs *)(TEGRA_APB_DMA_BASE + n)
|
||||
struct apb_dma_channel apb_dma_channels[] = {
|
||||
{ .num = 0, .regs = APB_DMA_OFFSET(0x1000) },
|
||||
{ .num = 1, .regs = APB_DMA_OFFSET(0x1040) },
|
||||
{ .num = 2, .regs = APB_DMA_OFFSET(0x1080) },
|
||||
{ .num = 3, .regs = APB_DMA_OFFSET(0x10c0) },
|
||||
{ .num = 4, .regs = APB_DMA_OFFSET(0x1100) },
|
||||
{ .num = 5, .regs = APB_DMA_OFFSET(0x1140) },
|
||||
{ .num = 6, .regs = APB_DMA_OFFSET(0x1180) },
|
||||
{ .num = 7, .regs = APB_DMA_OFFSET(0x11c0) },
|
||||
{ .num = 8, .regs = APB_DMA_OFFSET(0x1200) },
|
||||
{ .num = 9, .regs = APB_DMA_OFFSET(0x1240) },
|
||||
{ .num = 10, .regs = APB_DMA_OFFSET(0x1280) },
|
||||
{ .num = 11, .regs = APB_DMA_OFFSET(0x12c0) },
|
||||
{ .num = 12, .regs = APB_DMA_OFFSET(0x1300) },
|
||||
{ .num = 13, .regs = APB_DMA_OFFSET(0x1340) },
|
||||
{ .num = 14, .regs = APB_DMA_OFFSET(0x1380) },
|
||||
{ .num = 15, .regs = APB_DMA_OFFSET(0x13c0) },
|
||||
{ .num = 16, .regs = APB_DMA_OFFSET(0x1400) },
|
||||
{ .num = 17, .regs = APB_DMA_OFFSET(0x1440) },
|
||||
{ .num = 18, .regs = APB_DMA_OFFSET(0x1480) },
|
||||
{ .num = 19, .regs = APB_DMA_OFFSET(0x14c0) },
|
||||
{ .num = 20, .regs = APB_DMA_OFFSET(0x1500) },
|
||||
{ .num = 21, .regs = APB_DMA_OFFSET(0x1540) },
|
||||
{ .num = 22, .regs = APB_DMA_OFFSET(0x1580) },
|
||||
{ .num = 23, .regs = APB_DMA_OFFSET(0x15c0) },
|
||||
{ .num = 24, .regs = APB_DMA_OFFSET(0x1600) },
|
||||
{ .num = 25, .regs = APB_DMA_OFFSET(0x1640) },
|
||||
{ .num = 26, .regs = APB_DMA_OFFSET(0x1680) },
|
||||
{ .num = 27, .regs = APB_DMA_OFFSET(0x16c0) },
|
||||
{ .num = 28, .regs = APB_DMA_OFFSET(0x1700) },
|
||||
{ .num = 29, .regs = APB_DMA_OFFSET(0x1740) },
|
||||
{ .num = 30, .regs = APB_DMA_OFFSET(0x1780) },
|
||||
{ .num = 31, .regs = APB_DMA_OFFSET(0x17c0) },
|
||||
};
|
||||
|
||||
int dma_busy(struct apb_dma_channel * const channel)
|
||||
{
|
||||
/*
|
||||
* In continuous mode, the BSY_n bit in APB_DMA_STATUS and
|
||||
* BSY in APBDMACHAN_CHANNEL_n_STA_0 will remain set as '1' so long
|
||||
* as the channel is enabled. So for this function we'll use the
|
||||
* DMA_ACTIVITY bit.
|
||||
*/
|
||||
return read32(&channel->regs->sta) & APBDMACHAN_STA_DMA_ACTIVITY ? 1 : 0;
|
||||
}
|
||||
/* claim a DMA channel */
|
||||
struct apb_dma_channel * const dma_claim(void)
|
||||
{
|
||||
int i;
|
||||
struct apb_dma_channel_regs *regs = NULL;
|
||||
|
||||
/*
|
||||
* Set global enable bit, otherwise register access to channel
|
||||
* DMA registers will not be possible.
|
||||
*/
|
||||
setbits_le32(&apb_dma->command, APBDMA_COMMAND_GEN);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) {
|
||||
regs = apb_dma_channels[i].regs;
|
||||
|
||||
if (!apb_dma_channels[i].in_use) {
|
||||
u32 status = read32(®s->sta);
|
||||
if (status & (1 << i)) {
|
||||
/* FIXME: should this be fatal? */
|
||||
printk(BIOS_DEBUG, "%s: DMA channel %d busy?\n",
|
||||
__func__, i);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (i == ARRAY_SIZE(apb_dma_channels))
|
||||
return NULL;
|
||||
|
||||
apb_dma_channels[i].in_use = 1;
|
||||
return &apb_dma_channels[i];
|
||||
}
|
||||
|
||||
/* release a DMA channel */
|
||||
void dma_release(struct apb_dma_channel * const channel)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* FIXME: make this "thread" friendly */
|
||||
while (dma_busy(channel))
|
||||
;
|
||||
|
||||
channel->in_use = 0;
|
||||
|
||||
/* clear the global enable bit if no channels are in use */
|
||||
for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) {
|
||||
if (apb_dma_channels[i].in_use)
|
||||
return;
|
||||
}
|
||||
|
||||
clrbits_le32(&apb_dma->command, APBDMA_COMMAND_GEN);
|
||||
}
|
||||
|
||||
int dma_start(struct apb_dma_channel * const channel)
|
||||
{
|
||||
struct apb_dma_channel_regs *regs = channel->regs;
|
||||
|
||||
/* Set ENB bit for this channel */
|
||||
setbits_le32(®s->csr, APBDMACHAN_CSR_ENB);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dma_stop(struct apb_dma_channel * const channel)
|
||||
{
|
||||
struct apb_dma_channel_regs *regs = channel->regs;
|
||||
|
||||
/* Clear ENB bit for this channel */
|
||||
clrbits_le32(®s->csr, APBDMACHAN_CSR_ENB);
|
||||
|
||||
return 0;
|
||||
}
|
||||
Reference in New Issue
Block a user