These changes implement car in qemu. The implementation is in several
ways superior to v3, while lacking its completeness. But, one nice thing: no more included .S or .c files. It's all separate compilation. That should allow our Makefiles to work much better. Note that the current non-CAR implementation is the default and continues to work (tested FILO boot to Linux on both CAR and non-CAR). Index: src/mainboard/emulation/qemu-x86/Config.lb Change this to be sensitive to USE_DCACHE_RAM. All settings etc. that depend on this variable are grouped in one if, and the other parts (romcc etc.) are in the else. This change is a model of how we should be able to do other motherboards. Index: src/mainboard/emulation/qemu-x86/Options.lb add needed options. Index: src/mainboard/emulation/qemu-x86/failover.c remove code inclusion from this not-yet-used file. Index: src/mainboard/emulation/qemu-x86/rom.c This is the entry point for the rom-based code. Called stage1.c in v3. Index: src/lib/Config.lb change initobject to a .o from a .c; this fixed a build problem. Index: src/pc80/serial.c make uart_init non-static. Index: src/pc80/Config.lb add initobject Index: src/arch/i386/init/entry.S Entry point. Unify a bunch of files that were fiddly lttle includes. From v3. Index: src/arch/i386/init/ldscript.ld new file. The goal is to hang all init changes for CAR here, to minimize other changes to any other ldscript. Besides, putting this in init makes sense; entry and car are manage init. Index: src/arch/i386/init/car.S generic i386 car code from v3. Index: src/arch/i386/init/ldscript_fallback_cbfs.lb Fix what looks like a bug: this was not including the init.text section. Index: targets/emulation/qemu-x86/Config.lb push up the console loglevel. qemu is for debugging so we might as well get all the debugging we can. Index: targets/emulation/qemu-x86/Config-car.lb For CAR bullds. Signed-off-by: Ronald G. minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. minnich
committed by
Ronald G. Minnich
Ronald G. Minnich
parent
3ba18a67eb
commit
d41de2ea7a
@@ -1,3 +1,5 @@
|
||||
## we don't use USE_DCACHE_RAM by default
|
||||
default USE_DCACHE_RAM=0
|
||||
##
|
||||
## Compute the location and size of where this firmware image
|
||||
## (coreboot plus bootloader) will live in the boot rom chip.
|
||||
@@ -42,61 +44,78 @@ driver mainboard.o
|
||||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
#object reset.o
|
||||
|
||||
|
||||
## ALL dependencies for USE_DCACHE_RAM go here.
|
||||
## That way, later, we can simply yank them if we wish.
|
||||
## We include the old-fashioned entry code in the ! USE_DCACHE_RAM case.
|
||||
## we do not use failover yet in this case. This is a work in progress.
|
||||
if USE_DCACHE_RAM
|
||||
##
|
||||
##
|
||||
mainboardinit arch/i386/init/entry.S
|
||||
mainboardinit arch/i386/init/car.S
|
||||
ldscript /arch/i386/init/ldscript.ld
|
||||
|
||||
## The main code for the rom section is called rom.c
|
||||
initobject rom.o
|
||||
else
|
||||
##
|
||||
## Romcc output
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "$(MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu/enable_fpu.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
||||
## the id string will be in cbfs. We will expect flashrom to parse cbfs for the idstring in future.
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
##
|
||||
## Romcc output
|
||||
## end of USE_DCACHE_RAM bits.
|
||||
##
|
||||
makerule ./failover.E
|
||||
depends "$(MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "$(MAINBOARD)/failover.c ../romcc"
|
||||
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
|
||||
action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit coreboot entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where coreboot is entered)
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu/enable_fpu.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
|
||||
@@ -41,7 +41,10 @@ uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
|
||||
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses USE_DCACHE_RAM
|
||||
|
||||
uses DCACHE_RAM_BASE
|
||||
uses DCACHE_RAM_SIZE
|
||||
uses CONFIG_USE_INIT
|
||||
uses CONFIG_USE_PRINTK_IN_CAR
|
||||
|
||||
uses DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses MAXIMUM_CONSOLE_LOGLEVEL
|
||||
@@ -128,4 +131,12 @@ default CONFIG_ROM_PAYLOAD = 1
|
||||
default CC="$(CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## known-good settings for qemu
|
||||
default DCACHE_RAM_BASE=0x8f000
|
||||
default DCACHE_RAM_SIZE=0x1000
|
||||
|
||||
|
||||
|
||||
|
||||
end
|
||||
|
||||
@@ -1,16 +1,14 @@
|
||||
#define ASSEMBLY 1
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include "arch/romcc_io.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "cpu/x86/lapic/boot_cpu.c"
|
||||
/* no code inclusion allowed */
|
||||
//#include "pc80/mc146818rtc_early.c"
|
||||
//#include "cpu/x86/lapic/boot_cpu.c"
|
||||
|
||||
static void main(void)
|
||||
{
|
||||
/* for now, just always assume failure */
|
||||
|
||||
#if 0
|
||||
/* Is this a cpu reset? */
|
||||
if (cpu_init_detected()) {
|
||||
@@ -27,3 +25,4 @@ static void main(void)
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
30
src/mainboard/emulation/qemu-x86/rom.c
Normal file
30
src/mainboard/emulation/qemu-x86/rom.c
Normal file
@@ -0,0 +1,30 @@
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/hlt.h>
|
||||
#include <console/console.h>
|
||||
#include <cbfs.h>
|
||||
|
||||
/*
|
||||
*/
|
||||
void udelay(int usecs)
|
||||
{
|
||||
int i;
|
||||
for(i = 0; i < usecs; i++)
|
||||
outb(i&0xff, 0x80);
|
||||
}
|
||||
|
||||
void main(void)
|
||||
{
|
||||
int i;
|
||||
void uart_init(void);
|
||||
void (*start_address)();
|
||||
outb(5, 0x80);
|
||||
|
||||
uart_init();
|
||||
start_address = cbfs_load_stage("fallback/coreboot_ram");
|
||||
start_address();
|
||||
|
||||
}
|
||||
Reference in New Issue
Block a user