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soc/intel/xeon_sp: Add SATC PCI segment group support

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For every PCI segment group generate a new SATC header.
Allows to generate proper ACPI code when multiple PCI segment
groups are enabled.

TEST=Booted on ibm/sbp1 with multiple PCI segment groups.
      Properly generates multiple SATC headers.
TEST=intel/archercity CRB

Change-Id: I93b8ee05a7e6798e034f7a5da2c6883f0ee7a0e5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Patrick Rudolph 2024-03-08 09:49:15 +01:00
parent f95565311a
commit d425e881e3
1 changed files with 40 additions and 7 deletions
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47
src/soc/intel/xeon_sp/uncore_acpi.c
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@ -509,16 +509,49 @@ static unsigned long xeonsp_create_satc(unsigned long current, struct device *do
/* SoC Integrated Address Translation Cache */ /* SoC Integrated Address Translation Cache */
static unsigned long acpi_create_satc(unsigned long current) static unsigned long acpi_create_satc(unsigned long current)
{ {
const unsigned long tmp = current; unsigned long tmp = current, seg = ~0;
struct device *dev;
// Add the SATC header /*
current += acpi_create_dmar_satc(current, 0, 0); * Best case only PCI segment group count SATC headers are emitted, worst
* case for every SATC entry a new SATC header is being generated.
*
* The assumption made here is that the host bridges on a socket share the
* PCI segment group and thus only one SATC header needs to be emitted for
* a single socket.
* This is easier than to sort the host bridges by PCI segment group first
* and then generate one SATC header for every new segment.
*
* With this assumption the best case scenario should always be used.
*/
for (int socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) {
if (!soc_cpu_is_enabled(socket))
continue;
struct device *dev = NULL; dev = NULL;
while ((dev = dev_find_path(dev, DEVICE_PATH_DOMAIN))) while ((dev = dev_find_path(dev, DEVICE_PATH_DOMAIN))) {
current = xeonsp_create_satc(current, dev); /* Only add devices for the current socket */
if (iio_pci_domain_socket_from_dev(dev) != socket)
continue;
if (seg != dev->downstream->segment_group) {
// Close previous header
if (tmp != current)
acpi_dmar_satc_fixup(tmp, current);
seg = dev->downstream->segment_group;
tmp = current;
printk(BIOS_DEBUG, "[SATC Segment Header] "
"Flags: 0x%x, PCI segment group: %lx\n", 0, seg);
// Add the SATC header
current += acpi_create_dmar_satc(current, 0, seg);
}
current = xeonsp_create_satc(current, dev);
}
}
if (tmp != current)
acpi_dmar_satc_fixup(tmp, current);
acpi_dmar_satc_fixup(tmp, current);
return current; return current;
} }