From d462108ba8fc1a5bd8d9a4fd61e504718f1e0eb6 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 18 Mar 2024 17:10:57 +0530 Subject: [PATCH] cpu/x86/mtrr: Error out caching limitation during NEM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Improves user experience by highlighting a possibility of runtime hangs caused by unsupported WB caching during NEM. Recently we have encountered an issue on Intel platform and came to know about the NEM logical limitation where due to cache sets are not in power_on_two running into a runtime hang upon enabling WB caching. BUG=b:306677879 BRANCH=firmware-rex-15709.B TEST=Verified boot on google/ovis and google/rex (including Ovis with non-power-of-two cache configuration). Change-Id: Ic4fbef1fcc018856420428139683897634c9f85d Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/81336 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) Reviewed-by: Jérémy Compostella --- src/cpu/x86/mtrr/earlymtrr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index b6cc73751d..a55b2dcc98 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -37,6 +37,9 @@ void set_var_mtrr( /* FIXME: It only support 4G less range */ msr_t basem, maskm; + if (type == MTRR_TYPE_WRBACK && !is_cache_sets_power_of_two() && ENV_CACHE_AS_RAM) + printk(BIOS_ERR, "MTRR Error: Type %x may not be supported due to NEM limitation\n", + type); if (!IS_POWER_OF_2(size)) printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size); if (size < 4 * KiB)