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This patch gets the Epia-CN working without ACPI or APIC.

Browse Source 
All devices work, no irq storms. Enjoy.

Signed-off-by: Bari Ari <bari@onelabs.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3556 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Bari Ari
2008-09-01 01:48:07 +00:00
committed by Peter Stuge
parent 3153863567
commit d4759d0f22
8 changed files with 61 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/southbridge/via/vt8237r/vt8237r.c
View File

@@ -79,8 +79,6 @@ static void vt8237r_enable(struct device *dev)
pci_write_config8(dev, 0x51, sb->fn_ctrl_hi);
/* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */
/* Extend ROM decode to 1MB FFC00000 - FFFFFFFF */
pci_write_config8(dev, 0x41, 0x7f);
}
struct chip_operations southbridge_via_vt8237r_ops = {

26
src/southbridge/via/vt8237r/vt8237r_lpc.c
View File

@@ -244,10 +244,20 @@ static void vt8237r_init(struct device *dev)
enables |= 0x80;
pci_write_config8(dev, 0x6C, enables);
/* FIXME: Map 4MB of flash into the address space,
* this should be in CAR call.
/*
* ROM decode
* bit range
* 7 000E0000h-000EFFFFh
* 6 FFF00000h-FFF7FFFFh
* 5 FFE80000h-FFEFFFFFh
* 4 FFE00000h-FFE7FFFFh
* 3 FFD80000h-FFDFFFFFh
* 2 FFD00000h-FFD7FFFFh
* 1 FFC80000h-FFCFFFFFh
* 0 FFC00000h-FFC7FFFFh
* So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte.
*/
/* pci_write_config8(dev, 0x41, 0x7f); */
pci_write_config8(dev, 0x41, 0x7f);
/* Set bit 6 of 0x40 (I/O recovery time).
* IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so
@@ -271,8 +281,14 @@ static void vt8237r_init(struct device *dev)
/* ROM memory cycles go to LPC. */
pci_write_config8(dev, 0x59, 0x80);
/* Bypass APIC De-Assert Message, INTE#, INTF#, INTG#, INTH# as PCI. */
pci_write_config8(dev, 0x5B, 0xb);
/*
* bit meaning
* 3 Bypass APIC De-Assert Message (1=Enable)
* 1 possibly "INTE#, INTF#, INTG#, INTH# as PCI"
* bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
* 0 Dynamic Clock Gating Main Switch (1=Enable)
*/
pci_write_config8(dev, 0x5b, 0x9);
/* Set Read Pass Write Control Enable (force A2 from APIC FSB to low). */
pci_write_config8(dev, 0x48, 0x8c);