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Move pci_ops_mmconf from arch/x86/ to device/

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MMConf is not architecture specific. We also always provide a
pci_bus_default_ops() now if MMCONF_SUPPORT is selected.

Change-Id: I3f9b403da29d3fa81914cc1519710ba7d1bf2bb5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26062
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber
2018-05-04 16:29:13 +02:00
committed by Martin Roth
parent 3de303179a
commit d4ac11f6fa
5 changed files with 9 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/arch/x86/Makefile.inc
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@ -346,8 +346,7 @@ ramstage-y += memset.c
ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c
ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c
ramstage-y += pci_ops_conf1.c ramstage-y += pci_ops_conf1.c
ramstage-y += pci_ops.c ramstage-$(CONFIG_NO_MMCONF_SUPPORT) += pci_ops.c
ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c
ramstage-y += rdrand.c ramstage-y += rdrand.c
ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c

1
src/arch/x86/include/arch/pci_ops.h
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@ -17,7 +17,6 @@
#ifndef __SIMPLE_DEVICE__ #ifndef __SIMPLE_DEVICE__
extern const struct pci_bus_operations pci_cf8_conf1; extern const struct pci_bus_operations pci_cf8_conf1;
extern const struct pci_bus_operations pci_ops_mmconf;
#endif #endif

5
src/arch/x86/pci_ops.c
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@ -18,8 +18,5 @@
const struct pci_bus_operations *pci_bus_default_ops(struct device *dev) const struct pci_bus_operations *pci_bus_default_ops(struct device *dev)
{ {
if (IS_ENABLED(CONFIG_NO_MMCONF_SUPPORT)) return &pci_cf8_conf1;
return &pci_cf8_conf1;
return &pci_ops_mmconf;
} }

1
src/device/Makefile.inc
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@ -12,6 +12,7 @@ ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += azalia_device.c
ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += pnp_device.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += pnp_device.c
ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += pnp_device.c
ramstage-$(CONFIG_PCI) += pci_ops.c ramstage-$(CONFIG_PCI) += pci_ops.c
ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
ramstage-$(CONFIG_PCI) += pci_early.c ramstage-$(CONFIG_PCI) += pci_early.c
ramstage-$(CONFIG_PCI) += pci_rom.c ramstage-$(CONFIG_PCI) += pci_rom.c
ramstage-y += smbus_ops.c ramstage-y += smbus_ops.c

7
src/arch/x86/pci_ops_mmconf.c → src/device/pci_ops_mmconf.c
View File

@ -63,7 +63,7 @@ static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn,
write32(PCI_MMIO_ADDR(bus, devfn, where, 3), value); write32(PCI_MMIO_ADDR(bus, devfn, where, 3), value);
} }
const struct pci_bus_operations pci_ops_mmconf = { static const struct pci_bus_operations pci_ops_mmconf = {
.read8 = pci_mmconf_read_config8, .read8 = pci_mmconf_read_config8,
.read16 = pci_mmconf_read_config16, .read16 = pci_mmconf_read_config16,
.read32 = pci_mmconf_read_config32, .read32 = pci_mmconf_read_config32,
@ -71,3 +71,8 @@ const struct pci_bus_operations pci_ops_mmconf = {
.write16 = pci_mmconf_write_config16, .write16 = pci_mmconf_write_config16,
.write32 = pci_mmconf_write_config32, .write32 = pci_mmconf_write_config32,
}; };
const struct pci_bus_operations *pci_bus_default_ops(struct device *dev)
{
return &pci_ops_mmconf;
}