sb/intel/lynxpoint: Enable PCIe Clock PM and ASPM L1

Enable PCIe Clock power management and ASPM L1 substate by default. This
matches what Broadwell does.

Change-Id: Ic2bbcbc23d6bab0900d3e90ad8e2fbfa4aea3c16
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/southbridge/intel/lynxpoint/Kconfig

@@ -68,6 +68,12 @@ config PCIEXP_AER
 	bool
 	default y
 
+config PCIEXP_CLK_PM
+	default y
+
+config PCIEXP_L1_SUB_STATE
+	default y
+
 config SERIALIO_UART_CONSOLE
 	bool "Use SerialIO UART for console"
 	depends on INTEL_LYNXPOINT_LP