sravan/system76-coreboot
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trival. All the changes is about comment and spaces.

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1. Delete trailing white spaces.
2. Change the // comment to /* */.
3. Add some copyright header.
4. reindent.
5. delete multi blank lines.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao 2010-02-20 09:38:16 +00:00 committed by Zheng Bao
parent 3c970eee2a
commit d4c5c44d27
1 changed files with 36 additions and 36 deletions
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72
src/cpu/x86/lapic/lapic_cpu_init.c
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@ -19,15 +19,15 @@
#if CONFIG_RAMBASE >= 0x100000 #if CONFIG_RAMBASE >= 0x100000
/* This is a lot more paranoid now, since Linux can NOT handle /* This is a lot more paranoid now, since Linux can NOT handle
* being told there is a CPU when none exists. So any errors * being told there is a CPU when none exists. So any errors
* will return 0, meaning no CPU. * will return 0, meaning no CPU.
* *
* We actually handling that case by noting which cpus startup * We actually handling that case by noting which cpus startup
* and not telling anyone about the ones that dont. * and not telling anyone about the ones that dont.
*/ */
static unsigned long get_valid_start_eip(unsigned long orig_start_eip) static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
{ {
return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000 return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
} }
#endif #endif
@ -39,34 +39,34 @@ int lowmem_backup_size;
extern char _secondary_start[]; extern char _secondary_start[];
static void copy_secondary_start_to_1m_below(void) static void copy_secondary_start_to_1m_below(void)
{ {
#if CONFIG_RAMBASE >= 0x100000 #if CONFIG_RAMBASE >= 0x100000
extern char _secondary_start_end[]; extern char _secondary_start_end[];
unsigned long code_size; unsigned long code_size;
unsigned long start_eip; unsigned long start_eip;
/* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S
Also We need to copy the _secondary_start to the below 1M region Also We need to copy the _secondary_start to the below 1M region
*/ */
start_eip = get_valid_start_eip((unsigned long)_secondary_start); start_eip = get_valid_start_eip((unsigned long)_secondary_start);
code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start; code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
#if CONFIG_HAVE_ACPI_RESUME == 1 #if CONFIG_HAVE_ACPI_RESUME == 1
/* need to save it for RAM resume */ /* need to save it for RAM resume */
lowmem_backup_size = code_size; lowmem_backup_size = code_size;
lowmem_backup = malloc(code_size); lowmem_backup = malloc(code_size);
lowmem_backup_ptr = (char *)start_eip; lowmem_backup_ptr = (char *)start_eip;
if (lowmem_backup == NULL) if (lowmem_backup == NULL)
die("Out of backup memory\n"); die("Out of backup memory\n");
memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size); memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size);
#endif #endif
/* copy the _secondary_start to the ram below 1M*/ /* copy the _secondary_start to the ram below 1M*/
memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size); memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size); printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
#endif #endif
} }
@ -75,7 +75,7 @@ static int lapic_start_cpu(unsigned long apicid)
int timeout; int timeout;
unsigned long send_status, accept_status, start_eip; unsigned long send_status, accept_status, start_eip;
int j, num_starts, maxlvt; int j, num_starts, maxlvt;
/* /*
* Starting actual IPI sequence... * Starting actual IPI sequence...
*/ */
@ -90,7 +90,7 @@ static int lapic_start_cpu(unsigned long apicid)
/* /*
* Send IPI * Send IPI
*/ */
lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
| LAPIC_DM_INIT); | LAPIC_DM_INIT);
@ -104,7 +104,7 @@ static int lapic_start_cpu(unsigned long apicid)
if (timeout >= 1000) { if (timeout >= 1000) {
printk_err("CPU %ld: First apic write timed out. Disabling\n", printk_err("CPU %ld: First apic write timed out. Disabling\n",
apicid); apicid);
// too bad. // too bad.
printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
if (lapic_read(LAPIC_ESR)) { if (lapic_read(LAPIC_ESR)) {
printk_err("Try to reset ESR\n"); printk_err("Try to reset ESR\n");
@ -122,7 +122,7 @@ static int lapic_start_cpu(unsigned long apicid)
/* Send IPI */ /* Send IPI */
lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
printk_spew("Waiting for send to finish...\n"); printk_spew("Waiting for send to finish...\n");
timeout = 0; timeout = 0;
do { do {
@ -133,7 +133,7 @@ static int lapic_start_cpu(unsigned long apicid)
if (timeout >= 1000) { if (timeout >= 1000) {
printk_err("CPU %ld: Second apic write timed out. Disabling\n", printk_err("CPU %ld: Second apic write timed out. Disabling\n",
apicid); apicid);
// too bad. // too bad.
return 0; return 0;
} }
@ -244,10 +244,10 @@ int start_cpu(device_t cpu)
/* Get an index for the new processor */ /* Get an index for the new processor */
index = ++last_cpu_index; index = ++last_cpu_index;
/* Find end of the new processors stack */ /* Find end of the new processors stack */
#if (CONFIG_RAMTOP>0x100000) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1)) #if (CONFIG_RAMTOP>0x100000) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
if(index<1) { // only keep bsp on low if(index<1) { // only keep bsp on low
stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
} else { } else {
// for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu // for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
@ -265,7 +265,7 @@ int start_cpu(device_t cpu)
stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info); stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
#endif #endif
/* Record the index and which cpu structure we are using */ /* Record the index and which cpu structure we are using */
info = (struct cpu_info *)stack_end; info = (struct cpu_info *)stack_end;
info->index = index; info->index = index;
@ -339,7 +339,7 @@ void stop_this_cpu(void)
printk_spew("Deasserting INIT.\n"); printk_spew("Deasserting INIT.\n");
/* Deassert the LAPIC INIT */ /* Deassert the LAPIC INIT */
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id)); lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT); lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
printk_spew("Waiting for send to finish...\n"); printk_spew("Waiting for send to finish...\n");
@ -391,7 +391,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
} }
#if CONFIG_SERIAL_CPU_INIT == 0 #if CONFIG_SERIAL_CPU_INIT == 0
if(cpu==bsp_cpu) { if(cpu==bsp_cpu) {
continue; continue;
} }
#endif #endif
@ -437,7 +437,7 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
continue; continue;
} }
if (!cpu->initialized) { if (!cpu->initialized) {
printk_err("CPU 0x%02x did not initialize!\n", printk_err("CPU 0x%02x did not initialize!\n",
cpu->path.apic.apic_id); cpu->path.apic.apic_id);
} }
} }
@ -480,22 +480,22 @@ void initialize_cpus(struct bus *cpu_bus)
smm_init(); smm_init();
#endif #endif
cpus_ready_for_init(); cpus_ready_for_init();
#if CONFIG_SMP == 1 #if CONFIG_SMP == 1
#if CONFIG_SERIAL_CPU_INIT == 0 #if CONFIG_SERIAL_CPU_INIT == 0
/* start all aps at first, so we can init ECC all together */ /* start all aps at first, so we can init ECC all together */
start_other_cpus(cpu_bus, info->cpu); start_other_cpus(cpu_bus, info->cpu);
#endif #endif
#endif #endif
/* Initialize the bootstrap processor */ /* Initialize the bootstrap processor */
cpu_initialize(); cpu_initialize();
#if CONFIG_SMP == 1 #if CONFIG_SMP == 1
#if CONFIG_SERIAL_CPU_INIT == 1 #if CONFIG_SERIAL_CPU_INIT == 1
start_other_cpus(cpu_bus, info->cpu); start_other_cpus(cpu_bus, info->cpu);
#endif #endif
/* Now wait the rest of the cpus stop*/ /* Now wait the rest of the cpus stop*/
wait_other_cpus_stop(cpu_bus); wait_other_cpus_stop(cpu_bus);