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Via Epia-N and C3: Set ioapic delivery type in Kconfig

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The original comment says it's a Via C3 and not Epia requirement
to deliver IOAPIC interrupts on APIC serial bus.

Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/435
Tested-by: build bot (Jenkins)
This commit is contained in:
Patrick Georgi 2012-03-16 19:28:15 +01:00
parent 35e1c861f5
commit d4d5e4d3e1
3 changed files with 11 additions and 10 deletions
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8
src/arch/x86/Kconfig
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@ -88,4 +88,12 @@ config LITTLE_ENDIAN
bool bool
default !BIG_ENDIAN default !BIG_ENDIAN
config IOAPIC_INTERRUPTS_ON_FSB
bool
default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
bool
default n
endmenu endmenu

12
src/arch/x86/lib/ioapic.c
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@ -89,15 +89,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
ioapic_interrupts = 24; ioapic_interrupts = 24;
printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
// XXX this decision should probably be made elsewhere, and #ifdef CONFIG_IOAPIC_INTERRUPTS_ON_FSB
// it's the C3, not the EPIA this depends on.
#if CONFIG_EPIA_VT8237R_INIT
#define IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
#else
#define IOAPIC_INTERRUPTS_ON_FSB
#endif
#ifdef IOAPIC_INTERRUPTS_ON_FSB
/* /*
* For the Pentium 4 and above APICs deliver their interrupts * For the Pentium 4 and above APICs deliver their interrupts
* on the front side bus, enable that. * on the front side bus, enable that.
@ -106,7 +98,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
io_apic_write(ioapic_base, 0x03, io_apic_write(ioapic_base, 0x03,
io_apic_read(ioapic_base, 0x03) | (1 << 0)); io_apic_read(ioapic_base, 0x03) | (1 << 0));
#endif #endif
#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS #ifdef CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n");
io_apic_write(ioapic_base, 0x03, 0); io_apic_write(ioapic_base, 0x03, 0);
#endif #endif

1
src/cpu/via/c3/Kconfig
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@ -7,5 +7,6 @@ config CPU_SPECIFIC_OPTIONS
def_bool y def_bool y
select UDELAY_TSC select UDELAY_TSC
select MMX select MMX
select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
endif # CPU_VIA_C3 endif # CPU_VIA_C3