Via Epia-N and C3: Set ioapic delivery type in Kconfig

The original comment says it's a Via C3 and not Epia requirement
to deliver IOAPIC interrupts on APIC serial bus.

Change-Id: I73c55755e0ec1ac5756b4ee7ccdfc8eb93184e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/435
Tested-by: build bot (Jenkins)

src/arch/x86/Kconfig

@@ -88,4 +88,12 @@ config LITTLE_ENDIAN
 	bool
 	default !BIG_ENDIAN
 
+config IOAPIC_INTERRUPTS_ON_FSB
+	bool
+	default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
+
+config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
+	bool
+	default n
+
 endmenu

src/arch/x86/lib/ioapic.c

@@ -89,15 +89,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
 		ioapic_interrupts = 24;
 	printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
 
-// XXX this decision should probably be made elsewhere, and
-// it's the C3, not the EPIA this depends on.
-#if CONFIG_EPIA_VT8237R_INIT
-#define IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
-#else
-#define IOAPIC_INTERRUPTS_ON_FSB
-#endif
-
-#ifdef IOAPIC_INTERRUPTS_ON_FSB
+#ifdef CONFIG_IOAPIC_INTERRUPTS_ON_FSB
 	/*
 	 * For the Pentium 4 and above APICs deliver their interrupts
 	 * on the front side bus, enable that.
@@ -106,7 +98,7 @@ void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
 	io_apic_write(ioapic_base, 0x03,
 		      io_apic_read(ioapic_base, 0x03) | (1 << 0));
 #endif
-#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
+#ifdef CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
 	printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n");
 	io_apic_write(ioapic_base, 0x03, 0);
 #endif

src/cpu/via/c3/Kconfig

@@ -7,5 +7,6 @@ config CPU_SPECIFIC_OPTIONS
 	def_bool y
 	select UDELAY_TSC
 	select MMX
+	select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
 
 endif # CPU_VIA_C3