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intel/smm/gen1: Use smm_subregion()

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Change-Id: I371ed41f485b3143e47f091681198d6674928897
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34740
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-08-14 06:25:55 +03:00
parent b371e233eb
commit d53fd704f2
8 changed files with 62 additions and 107 deletions
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16
src/northbridge/intel/x4x/memmap.c
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@ -25,10 +25,10 @@
#include <device/pci_def.h>
#include <console/console.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/smm.h>
#include <northbridge/intel/x4x/x4x.h>
#include <program_loading.h>
#include <cpu/intel/smm_reloc.h>
#include <stage_cache.h>
/** Decodes used Graphics Mode Select (GMS) to kilobytes. */
u32 decode_igd_memory_size(const u32 gms)
@ -112,13 +112,13 @@ u8 decode_pciebar(u32 *const base, u32 *const len)
return 1;
}
u32 northbridge_get_tseg_size(void)
static size_t northbridge_get_tseg_size(void)
{
const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
return decode_tseg_size(esmramc);
}
u32 northbridge_get_tseg_base(void)
static uintptr_t northbridge_get_tseg_base(void)
{
return pci_read_config32(PCI_DEV(0, 0, 0), D0F0_TSEG);
}
@ -134,14 +134,10 @@ void *cbmem_top(void)
return (void *) top_of_ram;
}
void stage_cache_external_region(void **base, size_t *size)
void smm_region(uintptr_t *start, size_t *size)
{
/* The stage cache lives at the end of the TSEG region.
* The top of RAM is defined to be the TSEG base address.
*/
*size = CONFIG_SMM_RESERVED_SIZE;
*base = (void *)((uintptr_t)northbridge_get_tseg_base()
+ northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE);
*start = northbridge_get_tseg_base();
*size = northbridge_get_tseg_size();
}
void fill_postcar_frame(struct postcar_frame *pcf)