From d55060d2b094a86e4625e0835bc8cf9c74dd7b5b Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Mon, 6 Feb 2023 15:28:20 -0700 Subject: [PATCH] mb/system76/adl: Add Oryx Pro 11 as a variant Change-Id: Ib9cf93dc88cd51d429222540ce0721c6e5f4013a Signed-off-by: Tim Crawford --- src/mainboard/system76/adl/Kconfig | 13 +- src/mainboard/system76/adl/Kconfig.name | 3 + .../adl/variants/oryp11/board_info.txt | 2 + .../system76/adl/variants/oryp11/data.vbt | Bin 0 -> 8704 bytes .../system76/adl/variants/oryp11/gpio.c | 294 ++++++++++++++++++ .../system76/adl/variants/oryp11/gpio_early.c | 16 + .../system76/adl/variants/oryp11/hda_verb.c | 27 ++ .../variants/oryp11/include/variant/gpio.h | 13 + .../adl/variants/oryp11/overridetree.cb | 5 + .../system76/adl/variants/oryp11/romstage.c | 41 +++ 10 files changed, 413 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/system76/adl/variants/oryp11/board_info.txt create mode 100644 src/mainboard/system76/adl/variants/oryp11/data.vbt create mode 100644 src/mainboard/system76/adl/variants/oryp11/gpio.c create mode 100644 src/mainboard/system76/adl/variants/oryp11/gpio_early.c create mode 100644 src/mainboard/system76/adl/variants/oryp11/hda_verb.c create mode 100644 src/mainboard/system76/adl/variants/oryp11/include/variant/gpio.h create mode 100644 src/mainboard/system76/adl/variants/oryp11/overridetree.cb create mode 100644 src/mainboard/system76/adl/variants/oryp11/romstage.c diff --git a/src/mainboard/system76/adl/Kconfig b/src/mainboard/system76/adl/Kconfig index e7d12ce57a..1bb857c431 100644 --- a/src/mainboard/system76/adl/Kconfig +++ b/src/mainboard/system76/adl/Kconfig @@ -57,6 +57,14 @@ config BOARD_SYSTEM76_ORYP10 select EC_SYSTEM76_EC_COLOR_KEYBOARD select EC_SYSTEM76_EC_DGPU +config BOARD_SYSTEM76_ORYP11 + def_bool n + select BOARD_SYSTEM76_ADL_COMMON + select DRIVERS_GFX_NVIDIA + select EC_SYSTEM76_EC_COLOR_KEYBOARD + select EC_SYSTEM76_EC_DGPU + select SOC_INTEL_RAPTORLAKE + if BOARD_SYSTEM76_ADL_COMMON config MAINBOARD_DIR @@ -69,6 +77,7 @@ config VARIANT_DIR default "lemp11" if BOARD_SYSTEM76_LEMP11 default "oryp9" if BOARD_SYSTEM76_ORYP9 default "oryp10" if BOARD_SYSTEM76_ORYP10 + default "oryp11" if BOARD_SYSTEM76_ORYP11 config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -80,13 +89,14 @@ config MAINBOARD_PART_NUMBER default "lemp11" if BOARD_SYSTEM76_LEMP11 default "oryp9" if BOARD_SYSTEM76_ORYP9 default "oryp10" if BOARD_SYSTEM76_ORYP10 + default "oryp11" if BOARD_SYSTEM76_ORYP11 config MAINBOARD_SMBIOS_PRODUCT_NAME default "Darter Pro" if BOARD_SYSTEM76_DARP8 default "Galago Pro" if BOARD_SYSTEM76_GALP6 default "Gazelle" if BOARD_SYSTEM76_GAZE18_3050 default "Lemur Pro" if BOARD_SYSTEM76_LEMP11 - default "Oryx Pro" if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10 + default "Oryx Pro" if BOARD_SYSTEM76_ORYP9 || BOARD_SYSTEM76_ORYP10 || BOARD_SYSTEM76_ORYP11 config MAINBOARD_VERSION default "darp8" if BOARD_SYSTEM76_DARP8 @@ -95,6 +105,7 @@ config MAINBOARD_VERSION default "lemp11" if BOARD_SYSTEM76_LEMP11 default "oryp9" if BOARD_SYSTEM76_ORYP9 default "oryp10" if BOARD_SYSTEM76_ORYP10 + default "oryp11" if BOARD_SYSTEM76_ORYP11 config CBFS_SIZE default 0x1000000 diff --git a/src/mainboard/system76/adl/Kconfig.name b/src/mainboard/system76/adl/Kconfig.name index c68d240a8a..4970347921 100644 --- a/src/mainboard/system76/adl/Kconfig.name +++ b/src/mainboard/system76/adl/Kconfig.name @@ -15,3 +15,6 @@ config BOARD_SYSTEM76_ORYP9 config BOARD_SYSTEM76_ORYP10 bool "oryp10" + +config BOARD_SYSTEM76_ORYP11 + bool "oryp11" diff --git a/src/mainboard/system76/adl/variants/oryp11/board_info.txt b/src/mainboard/system76/adl/variants/oryp11/board_info.txt new file mode 100644 index 0000000000..37f71e1fa6 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp11/board_info.txt @@ -0,0 +1,2 @@ +Board name: oryp11 +Release year: 2023 diff --git a/src/mainboard/system76/adl/variants/oryp11/data.vbt b/src/mainboard/system76/adl/variants/oryp11/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..40fdfb28fe0331e7c8353e15f8252c7358cd4c0f GIT binary patch literal 8704 zcmeHMO-vg{6n^8M#c@q>1Wg>8(1Aq6&;V;gC_$)M^Orc`$2J5xQY0K=r==yqC8VNJ zC0q$roT@!lB&t*^YNZzSz^RvBd_?U94;-VYM@~^v_nX;`jcEu@)U+Y>TfLpx zd2haX@6FH7&K?=-9_6FKQ+<(vz}Y@7DNZW=R{Im~f2Z!?@W^;?U^Fn^JuuvJmOr3< z^nLB0_le?+9dP+n)fc=vo0#%O8u;M!#Nr8jZy!`bO15A_6j;L@eURAT1hY$DD_ z#!dyez$P$ zumJDLSPBBq=_cN0}^^ryKSl&g_{~R)E?fDs#1y?f{5N=nyH>ozOk<6 zAIw~v-AV6)PlF@i3*gJ(B=`n+0sIAc349y;1NcX92K+O4PaHrNIV@h(eHrBZg>pka zn|&%r>+%KZm~ml#MJ+CwZZJ1ed&N=8X7BDv>3sc=+YzfXYS*;S%XbQqi(8|Xoe|O% zoP5!P+?%S(AsFj7xx~t}GeZ0TX#uKNJ&WxIf~S4nD&Olsu#-(7bYU)R?}ge(OJPzq zHEB*&c!7!n%{6DQE(&3ehpXM1dlLfF?azSlUCZ2hxVm18F6C`tx*`!YWu*ukPM_4& zi50)5W%3A$*p$GFF?%tQyj(lB9HttzUpM#NpFsJsqpA(Nu2s1tMwF zvEzXasj_0c@OGur$(6%EXcV=GL|^FgmFr5|7m64Uw;IxG;e|Ribkp3o0l`XgpXAb% zVi43uZ8f$KS3O}l2BZyE3?|U?j!9`lxq)EkMR;+)n$jV@Uv;THqLyKUj`=7f*&)Y+ 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PWROK, NF1), // BATLOW_N + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_CFG_GPO(GPD2, 0, DEEP), // PCH_LAKE_WAKE# + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_NC(GPD6, NONE), + PAD_CFG_GPO(GPD7, 0, DEEP), // GPD_7 (Strap) + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // CNVI_SUSCLK + PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN# + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + PAD_NC(GPD12, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET# + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_NC(GPP_A9, NONE), + PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), // ESPI_ALRT0# + PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // GPIO4_GC6_NVVDD_EN_R + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, NONE), + PAD_NC(GPP_A14, NONE), + + /* ------- GPIO Group GPP_B ------- */ + _PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_NC(GPP_B1, NONE), + PAD_CFG_GPI(GPP_B2, NONE, DEEP), // CNVI_WAKE# + PAD_CFG_GPO(GPP_B3, 1, PLTRST), // PCH_BT_EN + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_NC(GPP_B11, NONE), + PAD_NC(GPP_B12, NONE), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1), // GPP_B18_PMCALERT# + PAD_NC(GPP_B19, NONE), + PAD_CFG_GPO(GPP_B20, 0, DEEP), // GPIO_LANRTD3 + _PAD_CFG_STRUCT(GPP_B21, 0x42880100, 0x0000), // GPP_B21_TBT_WAKE# + PAD_CFG_GPO(GPP_B22, 0, DEEP), // LAN_EC_RST# + PAD_CFG_GPI(GPP_B23, NONE, DEEP), // Crystal frequency strap + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_NC(GPP_C2, NONE), // PCH_PORT80_LED (TLS confidentiality strap) + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), // GPPB_I2C2_SDA (Pantone) + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), // GPPB_I2C2_SCL (Pantone) + PAD_NC(GPP_C5, NONE), // eSPI disable strap + PAD_CFG_GPI(GPP_C6, NONE, DEEP), // I2C3_SDA (PD controller) + PAD_CFG_GPI(GPP_C7, NONE, DEEP), // I2C3_SCL (PD controller) + PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // PCH_I2C_SDA + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // PCH_I2C_SCL + // GPP_C20 (UART2_RX) configured in bootblock + // GPP_C21 (UART2_TX) configured in bootblock + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_CFG_GPO(GPP_D3, 0, DEEP), // GFX_DETECT_STRAP + PAD_NC(GPP_D4, NONE), + PAD_CFG_GPO(GPP_D5, 0, DEEP), // M.2_BT_PCMFRM_CRF_RST_N + PAD_CFG_GPO(GPP_D6, 0, DEEP), // M.2_BT_PCMOUT_CLKREQ0 + PAD_CFG_GPO(GPP_D7, 0, DEEP), // M.2_BT_PCMIN + PAD_NC(GPP_D8, NONE), // M.2_BT_PCMCLK + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), // SSD_CLKREQ# + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_CFG_GPI(GPP_E2, NONE, DEEP), // SWI# + PAD_CFG_GPI(GPP_E3, NONE, DEEP), // SMI# + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + _PAD_CFG_STRUCT(GPP_E7, 0x80100100, 0x0000), // TP_ATTN# + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED# + PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0# + PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1# + PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2# + PAD_CFG_GPI(GPP_E12, NONE, DEEP), // USB_OC3# + PAD_NC(GPP_E13, NONE), + PAD_NC(GPP_E14, NONE), + PAD_CFG_GPO(GPP_E15, 0, DEEP), // ROM_I2C_EN + PAD_NC(GPP_E16, NONE), + PAD_CFG_GPI(GPP_E17, NONE, DEEP), // SB_KBCRST# + PAD_CFG_GPO(GPP_E18, 1, DEEP), // SB_BLON + PAD_NC(GPP_E19, NONE), + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, UP_20K, DEEP, NF1), // M.2_SSD_SATA_DET_N + PAD_NC(GPP_F1, NONE), + PAD_CFG_GPO(GPP_F2, 1, DEEP), // GPP_F2_TBT_RST# + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), // SSD_SATA_DEVSLP + PAD_NC(GPP_F6, NONE), + PAD_CFG_GPI(GPP_F7, NONE, DEEP), // INTP_8851 + PAD_CFG_GPI(GPP_F8, NONE, PLTRST), // GC6_FB_EN_PCH + // GPP_F9 (DGPU_PWR_EN) configured in bootblock + PAD_CFG_GPI(GPP_F10, NONE, DEEP), // Recovery strap + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_CFG_GPI(GPP_F15, NONE, DEEP), // K_SKTOCC_N + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP# + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NV_ENAVDD + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_G ------- */ + PAD_NC(GPP_G0, NONE), + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_CFG_GPI(GPP_G3, NONE, DEEP), // MB det (MB1/MB2) + PAD_CFG_GPI(GPP_G4, NONE, DEEP), // MB det (15"/17") + PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), // SLP_DRAM_N + PAD_CFG_GPI(GPP_G6, NONE, DEEP), // MB det (G-SYNC) + PAD_CFG_GPI(GPP_G7, NONE, DEEP), // MB det (Pantone) + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPI(GPP_H0, NONE, DEEP), // VAL_SV_ADVANCE_STRAP + PAD_NC(GPP_H1, NONE), + PAD_CFG_GPI(GPP_H2, NONE, DEEP), // WLAN_GPIO_WAKE_N + PAD_NC(GPP_H3, NONE), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // SSD_SATA_CLKREQ# + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // WLAN_CLKREQ# + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // CARD_CLKREQ# + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // GLAN_CLKREQ# + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // PEG_CLKREQ# + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // TBT_CLKREQ# + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), // eSPI flash sharing mode strap + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), // JTAG ODT disable strap + PAD_NC(GPP_H16, NONE), + PAD_NC(GPP_H17, NONE), + PAD_NC(GPP_H18, NONE), // 1.8V VCCPSPI strap + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_I ------- */ + _PAD_CFG_STRUCT(GPP_I0, 0x86880100, 0x0000), // DP_F_HPD + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // CPU_DP_B_HPD + _PAD_CFG_STRUCT(GPP_I2, 0x86880100, 0x0000), // HDMI_HPD + PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1), // CPU_DP_D_HPD + _PAD_CFG_STRUCT(GPP_I4, 0x86880100, 0x0000), // G_DP_DHPD_E + PAD_CFG_GPO(GPP_I5, 0, DEEP), // GPIO_TBT_RESET + PAD_NC(GPP_I6, NONE), + PAD_NC(GPP_I7, NONE), + PAD_NC(GPP_I8, NONE), + PAD_NC(GPP_I9, NONE), + PAD_NC(GPP_I10, NONE), + PAD_CFG_GPI(GPP_I11, NONE, DEEP), // USB_OC4# + PAD_CFG_GPI(GPP_I12, NONE, DEEP), // USB_OC5# + PAD_CFG_GPI(GPP_I13, NONE, DEEP), // USB_OC6# + PAD_CFG_GPI(GPP_I14, NONE, DEEP), // USB_OC7# + PAD_NC(GPP_I15, NONE), + PAD_NC(GPP_I16, NONE), + PAD_NC(GPP_I17, NONE), + PAD_NC(GPP_I18, NONE), // NO REBOOT strap + PAD_NC(GPP_I19, NONE), + PAD_NC(GPP_I20, NONE), + PAD_NC(GPP_I21, NONE), + PAD_NC(GPP_I22, NONE), // BOOT BIOS strap + + /* ------- GPIO Group GPP_J ------- */ + PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE_N + PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT_R + PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT_R + PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD + PAD_CFG_GPI(GPP_J8, NONE, DEEP), // VAL_TEST_SETUP_MENU + PAD_NC(GPP_J9, NONE), + PAD_NC(GPP_J10, NONE), + PAD_NC(GPP_J11, NONE), + + /* ------- GPIO Group GPP_K ------- */ + _PAD_CFG_STRUCT(GPP_K0, 0x42800100, 0x0000), // TBCIO_PLUG_EVENT# + PAD_NC(GPP_K1, NONE), + PAD_NC(GPP_K2, NONE), + PAD_CFG_GPO(GPP_K3, 1, PLTRST), // TBT_RTD3_PWR_EN_R + PAD_CFG_GPO(GPP_K4, 0, PWROK), // TBT_FORCE_PWR_R + PAD_NC(GPP_K5, NONE), + // GPP_K6 doesn't exist + // GPP_K7 doesn't exist + PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + // GPP_K10 doesn't exist + PAD_NC(GPP_K11, NONE), + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#_R + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), + PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD_R + PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // EDP_HPD + PAD_NC(GPP_R10, NONE), + PAD_NC(GPP_R11, NONE), + PAD_NC(GPP_R12, NONE), + PAD_NC(GPP_R13, NONE), + PAD_NC(GPP_R14, NONE), + PAD_NC(GPP_R15, NONE), + // GPP_R16 (DGPU_RST#_PCH) configured in bootblock + PAD_NC(GPP_R17, NONE), + PAD_NC(GPP_R18, NONE), + PAD_CFG_GPI(GPP_R19, NONE, DEEP), // SCI# + PAD_NC(GPP_R20, NONE), + PAD_NC(GPP_R21, NONE), + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), // GPPS_DMIC_CLK + PAD_NC(GPP_S5, NONE), // GPPS_DMIC_DATA + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/adl/variants/oryp11/gpio_early.c b/src/mainboard/system76/adl/variants/oryp11/gpio_early.c new file mode 100644 index 0000000000..fe6584546b --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp11/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RX + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TX +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/adl/variants/oryp11/hda_verb.c b/src/mainboard/system76/adl/variants/oryp11/hda_verb.c new file mode 100644 index 0000000000..d56d3c3231 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp11/hda_verb.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC1220 */ + 0x10ec1220, /* Vendor ID */ + 0x1558d502, /* Subsystem ID */ + 13, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1558d502), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x14, 0x0421101f), + AZALIA_PIN_CFG(0, 0x15, 0x40000000), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x04a11040), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x90170110), + AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d), + AZALIA_PIN_CFG(0, 0x1e, 0x04451150), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/adl/variants/oryp11/include/variant/gpio.h b/src/mainboard/system76/adl/variants/oryp11/include/variant/gpio.h new file mode 100644 index 0000000000..014f22df51 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp11/include/variant/gpio.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include + +#define DGPU_RST_N GPP_R16 +#define DGPU_PWR_EN GPP_F9 +#define DGPU_GC6 GPP_A11 +#define DGPU_SSID 0xd5021558 + +#endif diff --git a/src/mainboard/system76/adl/variants/oryp11/overridetree.cb b/src/mainboard/system76/adl/variants/oryp11/overridetree.cb new file mode 100644 index 0000000000..be627d3727 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp11/overridetree.cb @@ -0,0 +1,5 @@ +chip soc/intel/alderlake + device domain 0 on + subsystemid 0x1558 0xd502 inherit + end +end diff --git a/src/mainboard/system76/adl/variants/oryp11/romstage.c b/src/mainboard/system76/adl/variants/oryp11/romstage.c new file mode 100644 index 0000000000..082d0cbd10 --- /dev/null +++ b/src/mainboard/system76/adl/variants/oryp11/romstage.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR5, + .rcomp = { .resistor = 100, }, + .ect = true, + .LpDdrDqDqsReTraining = 1, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + const struct nvidia_gpu_config config = { + .power_gpio = DGPU_PWR_EN, + .reset_gpio = DGPU_RST_N, + .enable = true, + }; + // Enable dGPU power + nvidia_set_power(&config); + + // Set primary display to internal graphics + mupd->FspmConfig.PrimaryDisplay = 0; + + mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +}