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mb/google/puff: Use chipset dt reference names

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Use the references from the chipset devicetree as this makes the
comments superfluous.

Change-Id: I06a3acca0a72ff158a0143acc87d9479b2deb0d5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This commit is contained in:
Felix Singer
2024-01-17 21:51:07 +01:00
committed by Felix Singer
parent e04ee222d5
commit d571ea2eac
12 changed files with 345 additions and 290 deletions
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42
src/mainboard/google/puff/variants/ambassador/overridetree.cb
View File

@@ -208,7 +208,7 @@ chip soc/intel/cannonlake
register "sata_port[1].TxGen3DeEmph" = "0x20" register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on device domain 0 on
device pci 04.0 on device ref dptf on
chip drivers/intel/dptf chip drivers/intel/dptf
## Active Policy ## Active Policy
register "policies.active[0]" = "{.target=DPTF_CPU, register "policies.active[0]" = "{.target=DPTF_CPU,
@@ -272,8 +272,8 @@ chip soc/intel/cannonlake
device generic 0 on end device generic 0 on end
end end
end # DPTF 0x1903 end
device pci 14.0 on device ref xhci on
chip drivers/usb/acpi chip drivers/usb/acpi
device usb 0.0 on device usb 0.0 on
chip drivers/usb/acpi chip drivers/usb/acpi
@@ -353,29 +353,31 @@ chip soc/intel/cannonlake
end end
end end
end end
end # USB xHCI end
device pci 15.0 off device ref i2c0 off
# RFU - Reserved for Future Use. # RFU - Reserved for Future Use.
end # I2C #0 end
device pci 15.1 off end # I2C #1 device ref i2c1 off end
device pci 15.2 on device ref i2c2 on
# PCON PS175
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""1AF80175"" register "hid" = ""1AF80175""
register "name" = ""PS17"" register "name" = ""PS17""
register "desc" = ""Parade PS175"" register "desc" = ""Parade PS175""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #2, PCON PS175. end
device pci 15.3 on device ref i2c3 on
# Realtek RTD2142
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC2142"" register "hid" = ""10EC2142""
register "name" = ""RTD2"" register "name" = ""RTD2""
register "desc" = ""Realtek RTD2142"" register "desc" = ""Realtek RTD2142""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #3, Realtek RTD2142. end
device pci 16.0 on end # Management Engine Interface 1 device ref heci1 on end
device pci 19.0 on device ref i2c4 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC5682"" register "hid" = ""10EC5682""
register "name" = ""RT58"" register "name" = ""RT58""
@@ -388,9 +390,10 @@ chip soc/intel/cannonlake
register "property_list[0].integer" = "1" register "property_list[0].integer" = "1"
device i2c 1a on end device i2c 1a on end
end end
end #I2C #4 end
device pci 1a.0 on end # eMMC device ref emmc on end
device pci 1c.6 on device ref pcie_rp7 on
# RTL8111H Ethernet NIC
chip drivers/net chip drivers/net
register "customized_leds" = "0x05af" register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7 register "wake" = "GPE0_DW1_07" # GPP_C7
@@ -399,11 +402,12 @@ chip soc/intel/cannonlake
device pci 00.0 on end device pci 00.0 on end
end end
register "PcieRpSlotImplemented[6]" = "1" register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC end
device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) device ref pcie_rp11 on
# X2 NVMe
register "PcieRpSlotImplemented[10]" = "1" register "PcieRpSlotImplemented[10]" = "1"
end end
device pci 1e.3 off end # GSPI #1 device ref gspi1 off end
end end
# VR Settings Configuration for 4 Domains # VR Settings Configuration for 4 Domains

116
src/mainboard/google/puff/variants/baseboard/devicetree.cb
View File

@@ -198,14 +198,14 @@ chip soc/intel/cannonlake
device cpu_cluster 0 on end device cpu_cluster 0 on end
device domain 0 on device domain 0 on
device pci 00.0 on end # Host Bridge device ref system_agent on end
device pci 02.0 on end # Integrated Graphics Device device ref igpu on end
device pci 04.0 off end # SA Thermal device device ref dptf off end
device pci 05.0 off end # SA IPU device ref ipu off end
device pci 12.0 on end # Thermal Subsystem device ref thermal on end
device pci 12.5 off end # UFS SCS device ref ufs off end
device pci 12.6 off end # GSPI #2 device ref gspi2 off end
device pci 14.0 on device ref xhci on
chip drivers/usb/acpi chip drivers/usb/acpi
register "desc" = ""Root Hub"" register "desc" = ""Root Hub""
register "type" = "UPC_TYPE_HUB" register "type" = "UPC_TYPE_HUB"
@@ -281,78 +281,80 @@ chip soc/intel/cannonlake
end end
end end
end end
end # USB xHCI end
device pci 14.1 off end # USB xDCI (OTG) device ref xdci off end
device pci 14.3 on device ref cnvi_wifi on
chip drivers/wifi/generic chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0" register "wake" = "GPE0_PME_B0"
device generic 0 on end device generic 0 on end
end end
end # CNVi wifi end
device pci 14.5 on end # SDCard device ref sdxc on end
device pci 15.0 on end # I2C #0 device ref i2c0 on end
device pci 15.1 on end # I2C #1 device ref i2c1 on end
device pci 15.2 on end # I2C #2 device ref i2c2 on end
device pci 15.3 on end # I2C #3 device ref i2c3 on end
device pci 16.0 on end # Management Engine Interface 1 device ref heci1 on end
device pci 16.1 off end # Management Engine Interface 2 device ref heci2 off end
device pci 16.2 off end # Management Engine IDE-R device ref csme_ider off end
device pci 16.3 off end # Management Engine KT Redirection device ref csme_ktr off end
device pci 16.4 off end # Management Engine Interface 3 device ref heci3 off end
device pci 16.5 off end # Management Engine Interface 4 device ref heci4 off end
device pci 17.0 on end # SATA device ref sata on end
device pci 19.0 on end # I2C #4 device ref i2c4 on end
device pci 19.1 off end # I2C #5 device ref i2c5 off end
device pci 19.2 off end # UART #2 device ref uart2 off end
device pci 1a.0 off end # eMMC device ref emmc off end
device pci 1c.0 off end # PCI Express Port 1 (USB) device ref pcie_rp1 off end
device pci 1c.1 off end # PCI Express Port 2 (USB) device ref pcie_rp2 off end
device pci 1c.2 off end # PCI Express Port 3 (USB) device ref pcie_rp3 off end
device pci 1c.3 off end # PCI Express Port 4 (USB) device ref pcie_rp4 off end
device pci 1c.4 off end # PCI Express Port 5 (USB) device ref pcie_rp5 off end
device pci 1c.5 off end # PCI Express Port 6 device ref pcie_rp6 off end
device pci 1c.6 off end # PCI Express Port 7 device ref pcie_rp7 off end
device pci 1c.7 off end # PCI Express Port 8 device ref pcie_rp8 off end
device pci 1d.0 on # PCI Express Port 9 (X4 NVME) device ref pcie_rp9 on
# X4 NVME
register "PcieRpSlotImplemented[8]" = "1" register "PcieRpSlotImplemented[8]" = "1"
end end
device pci 1d.1 off end # PCI Express Port 10 device ref pcie_rp10 off end
device pci 1d.2 off end # PCI Express Port 11 device ref pcie_rp11 off end
device pci 1d.3 off end # PCI Express Port 12 device ref pcie_rp12 off end
device pci 1d.4 off end # PCI Express port 13 device ref pcie_rp13 off end
device pci 1d.5 on device ref pcie_rp14 on
# x4
chip drivers/wifi/generic chip drivers/wifi/generic
register "wake" = "GPE0_DW1_01" register "wake" = "GPE0_DW1_01"
device generic 0 on end device generic 0 on end
end end
register "PcieRpSlotImplemented[13]" = "1" register "PcieRpSlotImplemented[13]" = "1"
end # PCI Express Port 14 (x4) end
device pci 1e.0 on end # UART #0 device ref uart0 on end
device pci 1e.1 off end # UART #1 device ref uart1 off end
device pci 1e.2 on device ref gspi0 on
chip drivers/spi/acpi chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID" register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cr50"" register "compat_string" = ""google,cr50""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)"
device spi 0 on end device spi 0 on end
end end
end # GSPI #0 end
device pci 1e.3 on end # GSPI #1 device ref gspi1 on end
device pci 1f.0 on device ref lpc_espi on
chip ec/google/chromeec chip ec/google/chromeec
device pnp 0c09.0 on end device pnp 0c09.0 on end
end end
end # eSPI Interface end
device pci 1f.1 on end # P2SB device ref p2sb on end
device pci 1f.2 hidden end # Power Management Controller device ref pmc hidden end
device pci 1f.3 on device ref hda on
chip drivers/sof chip drivers/sof
register "jack_tplg" = "rt5682" register "jack_tplg" = "rt5682"
device generic 0 on end device generic 0 on end
end end
end # Intel HDA end
device pci 1f.4 on end # SMBus device ref smbus on end
device pci 1f.5 on end # PCH SPI device ref fast_spi on end
device pci 1f.6 off end # GbE device ref gbe off end
end end
end end

41
src/mainboard/google/puff/variants/dooly/overridetree.cb
View File

@@ -185,7 +185,7 @@ chip soc/intel/cannonlake
register "sata_port[1].TxGen3DeEmph" = "0x20" register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on device domain 0 on
device pci 04.0 on device ref dptf on
chip drivers/intel/dptf chip drivers/intel/dptf
## Active Policy ## Active Policy
register "policies.active[0]" = "{.target=DPTF_CPU, register "policies.active[0]" = "{.target=DPTF_CPU,
@@ -238,8 +238,8 @@ chip soc/intel/cannonlake
device generic 0 on end device generic 0 on end
end end
end # DPTF 0x1903 end
device pci 14.0 on device ref xhci on
chip drivers/usb/acpi chip drivers/usb/acpi
device usb 0.0 on device usb 0.0 on
chip drivers/usb/acpi chip drivers/usb/acpi
@@ -309,9 +309,10 @@ chip soc/intel/cannonlake
end end
end end
end end
end # USB xHCI end
device pci 14.5 off end # SDCard device ref sdxc off end
device pci 15.0 on device ref i2c0 on
# ALC1015
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC1015"" register "hid" = ""10EC1015""
register "desc" = ""Realtek SPK AMP L"" register "desc" = ""Realtek SPK AMP L""
@@ -324,10 +325,11 @@ chip soc/intel/cannonlake
register "uid" = "1" register "uid" = "1"
device i2c 29 on end device i2c 29 on end
end end
end # I2C #0 ALC1015 end
device pci 15.1 off end # I2C #1 device ref i2c1 off end
device pci 15.2 on end # I2C #2 LVDS device ref i2c2 on end # LVDS
device pci 15.3 on device ref i2c3 on
# Touchscreen
chip drivers/i2c/hid chip drivers/i2c/hid
register "generic.hid" = ""WDHT2002"" register "generic.hid" = ""WDHT2002""
register "generic.desc" = ""WDT Touchscreen"" register "generic.desc" = ""WDT Touchscreen""
@@ -340,9 +342,9 @@ chip soc/intel/cannonlake
register "hid_desc_reg_offset" = "0x20" register "hid_desc_reg_offset" = "0x20"
device i2c 2c on end device i2c 2c on end
end end
end # I2C #3 Touchscreen end
device pci 16.0 on end # Management Engine Interface 1 device ref heci1 on end
device pci 19.0 on device ref i2c4 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC5682"" register "hid" = ""10EC5682""
register "name" = ""RT58"" register "name" = ""RT58""
@@ -382,20 +384,21 @@ chip soc/intel/cannonlake
register "key.label" = ""mic_mute_switch_key"" register "key.label" = ""mic_mute_switch_key""
device generic 0 on end device generic 0 on end
end end
end #I2C #4 end
device pci 1a.0 on end # eMMC device ref emmc on end
device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) device ref pcie_rp11 on
# X2 NVMe
register "PcieRpSlotImplemented[10]" = "1" register "PcieRpSlotImplemented[10]" = "1"
end end
device pci 1e.3 off end # GSPI #1 device ref gspi1 off end
device pci 1f.3 on device ref hda on
chip drivers/sof chip drivers/sof
register "spkr_tplg" = "rt1015" register "spkr_tplg" = "rt1015"
register "jack_tplg" = "rt5682" register "jack_tplg" = "rt5682"
register "mic_tplg" = "_2ch_pdm0" register "mic_tplg" = "_2ch_pdm0"
device generic 0 on end device generic 0 on end
end end
end # Intel HDA end
end end
# VR Settings Configuration for 4 Domains # VR Settings Configuration for 4 Domains

42
src/mainboard/google/puff/variants/duffy/overridetree.cb
View File

@@ -269,7 +269,7 @@ chip soc/intel/cannonlake
register "sata_port[1].TxGen3DeEmph" = "0x20" register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on device domain 0 on
device pci 04.0 on device ref dptf on
chip drivers/intel/dptf chip drivers/intel/dptf
## Active Policy ## Active Policy
register "policies.active[0]" = "{.target=DPTF_CPU, register "policies.active[0]" = "{.target=DPTF_CPU,
@@ -331,8 +331,8 @@ chip soc/intel/cannonlake
device generic 0 on end device generic 0 on end
end end
end # DPTF 0x1903 end
device pci 14.0 on device ref xhci on
chip drivers/usb/acpi chip drivers/usb/acpi
device usb 0.0 on device usb 0.0 on
chip drivers/usb/acpi chip drivers/usb/acpi
@@ -412,29 +412,31 @@ chip soc/intel/cannonlake
end end
end end
end end
end # USB xHCI end
device pci 15.0 off device ref i2c0 off
# RFU - Reserved for Future Use. # RFU - Reserved for Future Use.
end # I2C #0 end
device pci 15.1 off end # I2C #1 device ref i2c1 off end
device pci 15.2 on device ref i2c2 on
# PCON PS175
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""1AF80175"" register "hid" = ""1AF80175""
register "name" = ""PS17"" register "name" = ""PS17""
register "desc" = ""Parade PS175"" register "desc" = ""Parade PS175""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #2, PCON PS175. end
device pci 15.3 on device ref i2c3 on
# Realtek RTD2142
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC2142"" register "hid" = ""10EC2142""
register "name" = ""RTD2"" register "name" = ""RTD2""
register "desc" = ""Realtek RTD2142"" register "desc" = ""Realtek RTD2142""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #3, Realtek RTD2142. end
device pci 16.0 on end # Management Engine Interface 1 device ref heci1 on end
device pci 19.0 on device ref i2c4 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC5682"" register "hid" = ""10EC5682""
register "name" = ""RT58"" register "name" = ""RT58""
@@ -447,9 +449,10 @@ chip soc/intel/cannonlake
register "property_list[0].integer" = "1" register "property_list[0].integer" = "1"
device i2c 1a on end device i2c 1a on end
end end
end #I2C #4 end
device pci 1a.0 on end # eMMC device ref emmc on end
device pci 1c.6 on device ref pcie_rp7 on
# RTL8111H Ethernet NIC
chip drivers/net chip drivers/net
register "customized_leds" = "0x05af" register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7 register "wake" = "GPE0_DW1_07" # GPP_C7
@@ -458,11 +461,12 @@ chip soc/intel/cannonlake
device pci 00.0 on end device pci 00.0 on end
end end
register "PcieRpSlotImplemented[6]" = "1" register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC end
device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) device ref pcie_rp11 on
# X2 NVMe
register "PcieRpSlotImplemented[10]" = "1" register "PcieRpSlotImplemented[10]" = "1"
end end
device pci 1e.3 off end # GSPI #1 device ref gspi1 off end
end end
# VR Settings Configuration for 4 Domains # VR Settings Configuration for 4 Domains

42
src/mainboard/google/puff/variants/faffy/overridetree.cb
View File

@@ -277,7 +277,7 @@ chip soc/intel/cannonlake
register "sata_port[1].TxGen3DeEmph" = "0x20" register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on device domain 0 on
device pci 04.0 on device ref dptf on
chip drivers/intel/dptf chip drivers/intel/dptf
## Passive Policy ## Passive Policy
register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)"
@@ -305,8 +305,8 @@ chip soc/intel/cannonlake
device generic 0 on end device generic 0 on end
end end
end # DPTF 0x1903 end
device pci 14.0 on device ref xhci on
chip drivers/usb/acpi chip drivers/usb/acpi
device usb 0.0 on device usb 0.0 on
chip drivers/usb/acpi chip drivers/usb/acpi
@@ -386,29 +386,31 @@ chip soc/intel/cannonlake
end end
end end
end end
end # USB xHCI end
device pci 15.0 off device ref i2c0 off
# RFU - Reserved for Future Use. # RFU - Reserved for Future Use.
end # I2C #0 end
device pci 15.1 off end # I2C #1 device ref i2c1 off end
device pci 15.2 on device ref i2c2 on
# PCON PS175
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""1AF80175"" register "hid" = ""1AF80175""
register "name" = ""PS17"" register "name" = ""PS17""
register "desc" = ""Parade PS175"" register "desc" = ""Parade PS175""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #2, PCON PS175. end
device pci 15.3 on device ref i2c3 on
# Realtek RTD2142
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC2142"" register "hid" = ""10EC2142""
register "name" = ""RTD2"" register "name" = ""RTD2""
register "desc" = ""Realtek RTD2142"" register "desc" = ""Realtek RTD2142""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #3, Realtek RTD2142. end
device pci 16.0 on end # Management Engine Interface 1 device ref heci1 on end
device pci 19.0 on device ref i2c4 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC5682"" register "hid" = ""10EC5682""
register "name" = ""RT58"" register "name" = ""RT58""
@@ -421,9 +423,10 @@ chip soc/intel/cannonlake
register "property_list[0].integer" = "1" register "property_list[0].integer" = "1"
device i2c 1a on end device i2c 1a on end
end end
end #I2C #4 end
device pci 1a.0 on end # eMMC device ref emmc on end
device pci 1c.6 on device ref pcie_rp7 on
# RTL8111H Ethernet NIC
chip drivers/net chip drivers/net
register "customized_leds" = "0x05af" register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7 register "wake" = "GPE0_DW1_07" # GPP_C7
@@ -432,11 +435,12 @@ chip soc/intel/cannonlake
device pci 00.0 on end device pci 00.0 on end
end end
register "PcieRpSlotImplemented[6]" = "1" register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC end
device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) device ref pcie_rp11 on
# X2 NVMe
register "PcieRpSlotImplemented[10]" = "1" register "PcieRpSlotImplemented[10]" = "1"
end end
device pci 1e.3 off end # GSPI #1 device ref gspi1 off end
end end
# VR Settings Configuration for 4 Domains # VR Settings Configuration for 4 Domains

60
src/mainboard/google/puff/variants/genesis/overridetree.cb
View File

@@ -243,7 +243,7 @@ chip soc/intel/cannonlake
register "sata_port[1].TxGen3DeEmph" = "0x20" register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on device domain 0 on
device pci 04.0 on device ref dptf on
chip drivers/intel/dptf chip drivers/intel/dptf
## Active Policy ## Active Policy
register "policies.active[0]" = "{.target=DPTF_CPU, register "policies.active[0]" = "{.target=DPTF_CPU,
@@ -304,8 +304,8 @@ chip soc/intel/cannonlake
device generic 0 on end device generic 0 on end
end end
end # DPTF 0x1903 end
device pci 14.0 on device ref xhci on
chip drivers/usb/acpi chip drivers/usb/acpi
device usb 0.0 on device usb 0.0 on
chip drivers/usb/acpi chip drivers/usb/acpi
@@ -383,29 +383,31 @@ chip soc/intel/cannonlake
end end
end end
end end
end # USB xHCI end
device pci 15.0 off device ref i2c0 off
# RFU - Reserved for Future Use. # RFU - Reserved for Future Use.
end # I2C #0 end
device pci 15.1 off end # I2C #1 device ref i2c1 off end
device pci 15.2 on device ref i2c2 on
# PCON PS175
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""1AF80175"" register "hid" = ""1AF80175""
register "name" = ""PS17"" register "name" = ""PS17""
register "desc" = ""Parade PS175"" register "desc" = ""Parade PS175""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #2, PCON PS175. end
device pci 15.3 on device ref i2c3 on
# Realtek RTD2142
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC2142"" register "hid" = ""10EC2142""
register "name" = ""RTD2"" register "name" = ""RTD2""
register "desc" = ""Realtek RTD2142"" register "desc" = ""Realtek RTD2142""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #3, Realtek RTD2142. end
device pci 16.0 on end # Management Engine Interface 1 device ref heci1 on end
device pci 19.0 on device ref i2c4 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC5682"" register "hid" = ""10EC5682""
register "name" = ""RT58"" register "name" = ""RT58""
@@ -418,9 +420,10 @@ chip soc/intel/cannonlake
register "property_list[0].integer" = "1" register "property_list[0].integer" = "1"
device i2c 1a on end device i2c 1a on end
end end
end #I2C #4 end
device pci 1a.0 off end # eMMC device ref emmc off end
device pci 1c.6 on # PCI Root Port 7 (LAN) device ref pcie_rp7 on
# LAN
chip drivers/net # RTL8111H Ethernet NIC chip drivers/net # RTL8111H Ethernet NIC
register "customized_leds" = "0x05af" register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7 register "wake" = "GPE0_DW1_07" # GPP_C7
@@ -429,24 +432,29 @@ chip soc/intel/cannonlake
device pci 00.0 on end device pci 00.0 on end
end end
end end
device pci 1c.7 on # PCI Root Port 8 (WLAN) device ref pcie_rp8 on
# WLAN
register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot
end end
device pci 1d.0 on # PCI Root Port 9 (TPU) device ref pcie_rp9 on
# TPU
register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot
end end
device pci 1d.1 off end # PCI Root Port 10 (Not connected) device ref pcie_rp10 off end
device pci 1d.2 on end # PCI Root Port 11 (TPU1) device ref pcie_rp11 on end
# TPU1
register "PcieRpSlotImplemented[10]" = "1" # M.2 Slot register "PcieRpSlotImplemented[10]" = "1" # M.2 Slot
device pci 1d.3 on end # PCI Root Port 12 (TPU0) device ref pcie_rp12 on end
# TPU0
register "PcieRpSlotImplemented[11]" = "1" # M.2 Slot register "PcieRpSlotImplemented[11]" = "1" # M.2 Slot
device pci 1d.4 on # PCI Root Port 13 (X4 i350 NIC) device ref pcie_rp13 on
# X4 i350 NIC
register "PcieRpSlotImplemented[12]" = "0" # Built-in register "PcieRpSlotImplemented[12]" = "0" # Built-in
end end
device pci 1d.5 on end # PCI Root Port 14 (non-root) device ref pcie_rp14 on end # non-root
device pci 1d.6 on end # PCI Root Port 15 (non-root) device ref pcie_rp15 on end # non-root
device pci 1d.7 on end # PCI Root Port 16 (non-root) device ref pcie_rp16 on end # non-root
device pci 1e.3 off end # GSPI #1 device ref gspi1 off end
end end
# VR Settings Configuration for 4 Domains # VR Settings Configuration for 4 Domains

42
src/mainboard/google/puff/variants/kaisa/overridetree.cb
View File

@@ -269,7 +269,7 @@ chip soc/intel/cannonlake
register "sata_port[1].TxGen3DeEmph" = "0x20" register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on device domain 0 on
device pci 04.0 on device ref dptf on
chip drivers/intel/dptf chip drivers/intel/dptf
## Active Policy ## Active Policy
register "policies.active[0]" = "{.target=DPTF_CPU, register "policies.active[0]" = "{.target=DPTF_CPU,
@@ -331,8 +331,8 @@ chip soc/intel/cannonlake
device generic 0 on end device generic 0 on end
end end
end # DPTF 0x1903 end
device pci 14.0 on device ref xhci on
chip drivers/usb/acpi chip drivers/usb/acpi
device usb 0.0 on device usb 0.0 on
chip drivers/usb/acpi chip drivers/usb/acpi
@@ -412,29 +412,31 @@ chip soc/intel/cannonlake
end end
end end
end end
end # USB xHCI end
device pci 15.0 off device ref i2c0 off
# RFU - Reserved for Future Use. # RFU - Reserved for Future Use.
end # I2C #0 end
device pci 15.1 off end # I2C #1 device ref i2c1 off end
device pci 15.2 on device ref i2c2 on
# PCON PS175
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""1AF80175"" register "hid" = ""1AF80175""
register "name" = ""PS17"" register "name" = ""PS17""
register "desc" = ""Parade PS175"" register "desc" = ""Parade PS175""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #2, PCON PS175. end
device pci 15.3 on device ref i2c3 on
# Realtek RTD2142
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC2142"" register "hid" = ""10EC2142""
register "name" = ""RTD2"" register "name" = ""RTD2""
register "desc" = ""Realtek RTD2142"" register "desc" = ""Realtek RTD2142""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #3, Realtek RTD2142. end
device pci 16.0 on end # Management Engine Interface 1 device ref heci1 on end
device pci 19.0 on device ref i2c4 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC5682"" register "hid" = ""10EC5682""
register "name" = ""RT58"" register "name" = ""RT58""
@@ -447,9 +449,10 @@ chip soc/intel/cannonlake
register "property_list[0].integer" = "1" register "property_list[0].integer" = "1"
device i2c 1a on end device i2c 1a on end
end end
end #I2C #4 end
device pci 1a.0 on end # eMMC device ref emmc on end
device pci 1c.6 on device ref pcie_rp7 on
# RTL8111H Ethernet NIC
chip drivers/net chip drivers/net
register "customized_leds" = "0x05af" register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7 register "wake" = "GPE0_DW1_07" # GPP_C7
@@ -458,11 +461,12 @@ chip soc/intel/cannonlake
device pci 00.0 on end device pci 00.0 on end
end end
register "PcieRpSlotImplemented[6]" = "1" register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC end
device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) device ref pcie_rp11 on
# X2 NVMe
register "PcieRpSlotImplemented[10]" = "1" register "PcieRpSlotImplemented[10]" = "1"
end end
device pci 1e.3 off end # GSPI #1 device ref gspi1 off end
end end
# VR Settings Configuration for 4 Domains # VR Settings Configuration for 4 Domains

64
src/mainboard/google/puff/variants/moonbuggy/overridetree.cb
View File

@@ -243,7 +243,7 @@ chip soc/intel/cannonlake
register "sata_port[1].TxGen3DeEmph" = "0x20" register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on device domain 0 on
device pci 04.0 on device ref dptf on
chip drivers/intel/dptf chip drivers/intel/dptf
## Active Policy ## Active Policy
register "policies.active[0]" = "{.target=DPTF_CPU, register "policies.active[0]" = "{.target=DPTF_CPU,
@@ -304,8 +304,8 @@ chip soc/intel/cannonlake
device generic 0 on end device generic 0 on end
end end
end # DPTF 0x1903 end
device pci 14.0 on device ref xhci on
chip drivers/usb/acpi chip drivers/usb/acpi
device usb 0.0 on device usb 0.0 on
chip drivers/usb/acpi chip drivers/usb/acpi
@@ -385,29 +385,31 @@ chip soc/intel/cannonlake
end end
end end
end end
end # USB xHCI end
device pci 15.0 off device ref i2c0 off
# RFU - Reserved for Future Use. # RFU - Reserved for Future Use.
end # I2C #0 end
device pci 15.1 off end # I2C #1 device ref i2c1 off end
device pci 15.2 on device ref i2c2 on
# PCON PS175
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""1AF80175"" register "hid" = ""1AF80175""
register "name" = ""PS17"" register "name" = ""PS17""
register "desc" = ""Parade PS175"" register "desc" = ""Parade PS175""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #2, PCON PS175. end
device pci 15.3 on device ref i2c3 on
# Realtek RTD2142
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC2142"" register "hid" = ""10EC2142""
register "name" = ""RTD2"" register "name" = ""RTD2""
register "desc" = ""Realtek RTD2142"" register "desc" = ""Realtek RTD2142""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #3, Realtek RTD2142. end
device pci 16.0 on end # Management Engine Interface 1 device ref heci1 on end
device pci 19.0 on device ref i2c4 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC5682"" register "hid" = ""10EC5682""
register "name" = ""RT58"" register "name" = ""RT58""
@@ -420,9 +422,10 @@ chip soc/intel/cannonlake
register "property_list[0].integer" = "1" register "property_list[0].integer" = "1"
device i2c 1a on end device i2c 1a on end
end end
end #I2C #4 end
device pci 1a.0 off end # eMMC device ref emmc off end
device pci 1c.6 on # PCI Root Port 7 (LAN) device ref pcie_rp7 on
# LAN
chip drivers/net # RTL8111H Ethernet NIC chip drivers/net # RTL8111H Ethernet NIC
register "customized_leds" = "0x05af" register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7 register "wake" = "GPE0_DW1_07" # GPP_C7
@@ -431,26 +434,31 @@ chip soc/intel/cannonlake
device pci 00.0 on end device pci 00.0 on end
end end
end end
device pci 1c.7 on # PCI Root Port 8 (WLAN) device ref pcie_rp8 on
# WLAN
register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot
end end
device pci 1d.0 on # PCI Root Port 9 (TPU) device ref pcie_rp9 on
# TPU
register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot
end end
device pci 1d.1 off end # PCI Root Port 10 (Not connected) device ref pcie_rp10 off end
device pci 1d.2 on end # PCI Root Port 11 (TPU1) device ref pcie_rp11 on end
# TPU1
register "PcieRpSlotImplemented[10]" = "1" # M.2 Slot register "PcieRpSlotImplemented[10]" = "1" # M.2 Slot
device pci 1d.3 on end # PCI Root Port 12 (TPU0) device ref pcie_rp12 on end
# TPU0
register "PcieRpSlotImplemented[11]" = "1" # M.2 Slot register "PcieRpSlotImplemented[11]" = "1" # M.2 Slot
device pci 1d.4 on # PCI Root Port 13 (X4 i350 NIC) device ref pcie_rp13 on
# X4 i350 NIC
register "PcieRpSlotImplemented[12]" = "0" # Built-in register "PcieRpSlotImplemented[12]" = "0" # Built-in
end end
device pci 1d.5 on end # PCI Root Port 14 (non-root) device ref pcie_rp14 on end # non-root
device pci 1d.6 on end # PCI Root Port 15 (non-root) device ref pcie_rp15 on end # non-root
device pci 1d.7 on end # PCI Root Port 16 (non-root) device ref pcie_rp16 on end # non-root
device pci 1e.0 on end # UART #0 device ref uart0 on end
device pci 1e.1 on end # UART #1 device ref uart1 on end
device pci 1e.3 off end # GSPI #1 device ref gspi1 off end
end end
# VR Settings Configuration for 4 Domains # VR Settings Configuration for 4 Domains

42
src/mainboard/google/puff/variants/noibat/overridetree.cb
View File

@@ -192,7 +192,7 @@ chip soc/intel/cannonlake
register "sata_port[1].TxGen3DeEmph" = "0x20" register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on device domain 0 on
device pci 04.0 on device ref dptf on
chip drivers/intel/dptf chip drivers/intel/dptf
## Active Policy ## Active Policy
register "policies.active[0]" = "{.target=DPTF_CPU, register "policies.active[0]" = "{.target=DPTF_CPU,
@@ -254,8 +254,8 @@ chip soc/intel/cannonlake
device generic 0 on end device generic 0 on end
end end
end # DPTF 0x1903 end
device pci 14.0 on device ref xhci on
chip drivers/usb/acpi chip drivers/usb/acpi
device usb 0.0 on device usb 0.0 on
chip drivers/usb/acpi chip drivers/usb/acpi
@@ -323,29 +323,31 @@ chip soc/intel/cannonlake
end end
end end
end end
end # USB xHCI end
device pci 15.0 off device ref i2c0 off
# RFU - Reserved for Future Use. # RFU - Reserved for Future Use.
end # I2C #0 end
device pci 15.1 off end # I2C #1 device ref i2c1 off end
device pci 15.2 on device ref i2c2 on
# PCON PS175
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""1AF80175"" register "hid" = ""1AF80175""
register "name" = ""PS17"" register "name" = ""PS17""
register "desc" = ""Parade PS175"" register "desc" = ""Parade PS175""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #2, PCON PS175. end
device pci 15.3 on device ref i2c3 on
# Realtek RTD2142
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC2142"" register "hid" = ""10EC2142""
register "name" = ""RTD2"" register "name" = ""RTD2""
register "desc" = ""Realtek RTD2142"" register "desc" = ""Realtek RTD2142""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #3, Realtek RTD2142. end
device pci 16.0 on end # Management Engine Interface 1 device ref heci1 on end
device pci 19.0 on device ref i2c4 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC5682"" register "hid" = ""10EC5682""
register "name" = ""RT58"" register "name" = ""RT58""
@@ -358,9 +360,10 @@ chip soc/intel/cannonlake
register "property_list[0].integer" = "1" register "property_list[0].integer" = "1"
device i2c 1a on end device i2c 1a on end
end end
end #I2C #4 end
device pci 1a.0 on end # eMMC device ref emmc on end
device pci 1c.6 on device ref pcie_rp7 on
# RTL8111H Ethernet NIC
chip drivers/net chip drivers/net
register "customized_leds" = "0x05af" register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7 register "wake" = "GPE0_DW1_07" # GPP_C7
@@ -369,11 +372,12 @@ chip soc/intel/cannonlake
device pci 00.0 on end device pci 00.0 on end
end end
register "PcieRpSlotImplemented[6]" = "1" register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC end
device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) device ref pcie_rp11 on
# X2 NVMe
register "PcieRpSlotImplemented[10]" = "1" register "PcieRpSlotImplemented[10]" = "1"
end end
device pci 1e.3 off end # GSPI #1 device ref gspi1 off end
end end
# VR Settings Configuration for 4 Domains # VR Settings Configuration for 4 Domains

42
src/mainboard/google/puff/variants/puff/overridetree.cb
View File

@@ -202,7 +202,7 @@ chip soc/intel/cannonlake
register "sata_port[1].TxGen3DeEmph" = "0x20" register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on device domain 0 on
device pci 04.0 on device ref dptf on
chip drivers/intel/dptf chip drivers/intel/dptf
## Active Policy ## Active Policy
register "policies.active[0]" = "{.target=DPTF_CPU, register "policies.active[0]" = "{.target=DPTF_CPU,
@@ -266,8 +266,8 @@ chip soc/intel/cannonlake
device generic 0 on end device generic 0 on end
end end
end # DPTF 0x1903 end
device pci 14.0 on device ref xhci on
chip drivers/usb/acpi chip drivers/usb/acpi
device usb 0.0 on device usb 0.0 on
chip drivers/usb/acpi chip drivers/usb/acpi
@@ -347,29 +347,31 @@ chip soc/intel/cannonlake
end end
end end
end end
end # USB xHCI end
device pci 15.0 off device ref i2c0 off
# RFU - Reserved for Future Use. # RFU - Reserved for Future Use.
end # I2C #0 end
device pci 15.1 off end # I2C #1 device ref i2c1 off end
device pci 15.2 on device ref i2c2 on
# PCON PS175
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""1AF80175"" register "hid" = ""1AF80175""
register "name" = ""PS17"" register "name" = ""PS17""
register "desc" = ""Parade PS175"" register "desc" = ""Parade PS175""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #2, PCON PS175. end
device pci 15.3 on device ref i2c3 on
# Realtek RTD2142
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC2142"" register "hid" = ""10EC2142""
register "name" = ""RTD2"" register "name" = ""RTD2""
register "desc" = ""Realtek RTD2142"" register "desc" = ""Realtek RTD2142""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #3, Realtek RTD2142. end
device pci 16.0 on end # Management Engine Interface 1 device ref heci1 on end
device pci 19.0 on device ref i2c4 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC5682"" register "hid" = ""10EC5682""
register "name" = ""RT58"" register "name" = ""RT58""
@@ -382,9 +384,10 @@ chip soc/intel/cannonlake
register "property_list[0].integer" = "1" register "property_list[0].integer" = "1"
device i2c 1a on end device i2c 1a on end
end end
end #I2C #4 end
device pci 1a.0 on end # eMMC device ref emmc on end
device pci 1c.6 on device ref pcie_rp7 on
# RTL8111H Ethernet NIC
chip drivers/net chip drivers/net
register "customized_leds" = "0x05af" register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7 register "wake" = "GPE0_DW1_07" # GPP_C7
@@ -393,11 +396,12 @@ chip soc/intel/cannonlake
device pci 00.0 on end device pci 00.0 on end
end end
register "PcieRpSlotImplemented[6]" = "1" register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC end
device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) device ref pcie_rp11 on
# X2 NVMe
register "PcieRpSlotImplemented[10]" = "1" register "PcieRpSlotImplemented[10]" = "1"
end end
device pci 1e.3 off end # GSPI #1 device ref gspi1 off end
end end
# VR Settings Configuration for 4 Domains # VR Settings Configuration for 4 Domains

58
src/mainboard/google/puff/variants/scout/overridetree.cb
View File

@@ -235,7 +235,7 @@ chip soc/intel/cannonlake
register "sata_port[1].TxGen3DeEmph" = "0x20" register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on device domain 0 on
device pci 04.0 on device ref dptf on
chip drivers/intel/dptf chip drivers/intel/dptf
## Active Policy ## Active Policy
register "policies.active[0]" = "{.target=DPTF_CPU, register "policies.active[0]" = "{.target=DPTF_CPU,
@@ -298,8 +298,8 @@ chip soc/intel/cannonlake
device generic 0 on end device generic 0 on end
end end
end # DPTF 0x1903 end
device pci 14.0 on device ref xhci on
chip drivers/usb/acpi chip drivers/usb/acpi
device usb 0.0 on device usb 0.0 on
chip drivers/usb/acpi chip drivers/usb/acpi
@@ -377,11 +377,12 @@ chip soc/intel/cannonlake
end end
end end
end end
end # USB xHCI end
device pci 15.0 off device ref i2c0 off
# RFU - Reserved for Future Use. # RFU - Reserved for Future Use.
end # I2C #0 end
device pci 15.1 on # I2C #1, USI (Touch screen) device ref i2c1 on
# USI (Touch screen)
chip drivers/i2c/hid chip drivers/i2c/hid
register "generic.hid" = ""ILTK0001"" register "generic.hid" = ""ILTK0001""
register "generic.desc" = ""ILITEK Touchscreen"" register "generic.desc" = ""ILITEK Touchscreen""
@@ -395,13 +396,14 @@ chip soc/intel/cannonlake
device i2c 41 on end device i2c 41 on end
end end
end end
device pci 15.2 on end # I2C #2, SCALER device ref i2c2 on end # SCALER
device pci 15.3 on end # I2C #3, TPU device ref i2c3 on end # TPU
device pci 16.0 on end # Management Engine Interface 1 device ref heci1 on end
device pci 19.0 off end # I2C #4 device ref i2c4 off end
device pci 1a.0 on end # eMMC device ref emmc on end
device pci 1c.6 on # PCI Root Port 7 (LAN) device ref pcie_rp7 on
chip drivers/net # RTL8111H Ethernet NIC # RTL8111H Ethernet NIC
chip drivers/net
register "customized_leds" = "0x05af" register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7 register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0" register "device_index" = "0"
@@ -409,26 +411,30 @@ chip soc/intel/cannonlake
device pci 00.0 on end device pci 00.0 on end
end end
end end
device pci 1c.7 on # PCI Root Port 8 (WLAN) device ref pcie_rp8 on
# WLAN
register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot
end end
device pci 1d.0 on # PCI Root Port 9 (SSD) device ref pcie_rp9 on
# SSD
register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot
end end
device pci 1d.1 off end # PCI Root Port 10 (Not connected) device ref pcie_rp10 off end
device pci 1d.2 off end # PCI Root Port 11 (Not connected) device ref pcie_rp11 off end
device pci 1d.3 off end # PCI Root Port 12 (Not connected) device ref pcie_rp12 off end
device pci 1d.4 on # PCI Root Port 13 (TPU0) device ref pcie_rp13 on
# TPU0
register "PcieRpSlotImplemented[12]" = "1" # M.2 Slot register "PcieRpSlotImplemented[12]" = "1" # M.2 Slot
end end
device pci 1d.5 on # PCI Root Port 14 (TPU1) device ref pcie_rp14 on
# TPU1
register "PcieRpSlotImplemented[13]" = "1" # M.2 Slot register "PcieRpSlotImplemented[13]" = "1" # M.2 Slot
end end
device pci 1d.6 on end # PCI Root Port 15 (non-root) device ref pcie_rp15 on end # non-root
device pci 1d.7 on end # PCI Root Port 16 (non-root) device ref pcie_rp16 on end # non-root
device pci 1e.0 on end # UART #0 device ref uart0 on end
device pci 1e.1 on end # UART #1 device ref uart1 on end
device pci 1e.3 off end # GSPI #1 device ref gspi1 off end
end end
# VR Settings Configuration for 4 Domains # VR Settings Configuration for 4 Domains

44
src/mainboard/google/puff/variants/wyvern/overridetree.cb
View File

@@ -203,7 +203,7 @@ chip soc/intel/cannonlake
register "sata_port[1].TxGen3DeEmph" = "0x20" register "sata_port[1].TxGen3DeEmph" = "0x20"
device domain 0 on device domain 0 on
device pci 04.0 on device ref dptf on
chip drivers/intel/dptf chip drivers/intel/dptf
## Active Policy ## Active Policy
register "policies.active[0]" = "{.target=DPTF_CPU, register "policies.active[0]" = "{.target=DPTF_CPU,
@@ -267,8 +267,8 @@ chip soc/intel/cannonlake
device generic 0 on end device generic 0 on end
end end
end # DPTF 0x1903 end
device pci 14.0 on device ref xhci on
chip drivers/usb/acpi chip drivers/usb/acpi
device usb 0.0 on device usb 0.0 on
chip drivers/usb/acpi chip drivers/usb/acpi
@@ -348,29 +348,31 @@ chip soc/intel/cannonlake
end end
end end
end end
end # USB xHCI end
device pci 15.0 off device ref i2c0 off
# RFU - Reserved for Future Use. # RFU - Reserved for Future Use.
end # I2C #0 end
device pci 15.1 off end # I2C #1 device ref i2c1 off end
device pci 15.2 on device ref i2c2 on
# PCON PS175
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""1AF80175"" register "hid" = ""1AF80175""
register "name" = ""PS17"" register "name" = ""PS17""
register "desc" = ""Parade PS175"" register "desc" = ""Parade PS175""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #2, PCON PS175. end
device pci 15.3 on device ref i2c3 on
# Realtek RTD2142
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC2142"" register "hid" = ""10EC2142""
register "name" = ""RTD2"" register "name" = ""RTD2""
register "desc" = ""Realtek RTD2142"" register "desc" = ""Realtek RTD2142""
device i2c 4a on end device i2c 4a on end
end end
end # I2C #3, Realtek RTD2142. end
device pci 16.0 on end # Management Engine Interface 1 device ref heci1 on end
device pci 19.0 on device ref i2c4 on
chip drivers/i2c/generic chip drivers/i2c/generic
register "hid" = ""10EC5682"" register "hid" = ""10EC5682""
register "name" = ""RT58"" register "name" = ""RT58""
@@ -383,22 +385,24 @@ chip soc/intel/cannonlake
register "property_list[0].integer" = "1" register "property_list[0].integer" = "1"
device i2c 1a on end device i2c 1a on end
end end
end #I2C #4 end
device pci 1a.0 on end # eMMC device ref emmc on end
device pci 1c.6 on device ref pcie_rp7 on
# RTL8111H Ethernet NIC
chip drivers/net chip drivers/net
register "customized_leds" = "0x05af" register "customized_leds" = "0x05af"
register "wake" = "GPE0_DW1_07" # GPP_C7 register "wake" = "GPE0_DW1_07" # GPP_C7
register "device_index" = "0" register "device_index" = "0"
register "enable_aspm_l1_2" = "1" register "enable_aspm_l1_2" = "1"
device pci 00.0 on end device ref system_agent on end
end end
register "PcieRpSlotImplemented[6]" = "1" register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC end
device pci 1d.2 on # PCI Express Port 11 (X2 NVMe) device ref pcie_rp11 on
# X2 NVMe
register "PcieRpSlotImplemented[10]" = "1" register "PcieRpSlotImplemented[10]" = "1"
end end
device pci 1e.3 off end # GSPI #1 device ref gspi1 off end
end end
# VR Settings Configuration for 4 Domains # VR Settings Configuration for 4 Domains